Ex Parte Michaelis

Board of Patent Appeals and Interferences

Oct 25, 2007

10400856 (B.P.A.I. Oct. 25, 2007)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
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Ex parte SCOTT LYNN MICHAELIS
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Appeal 2007-1968
Application 10/400,856
Technology Center 2100
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Decided: October 25, 2007
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Before JAMES D. THOMAS, JEAN R. HOMERE, and
JOHN A. JEFFERY, Administrative Patent Judges.

THOMAS, Administrative Patent Judge.

DECISION ON APPEAL
This appeal involves claims 1 through 20. We have jurisdiction under
35 U.S.C. §§ 6(b) and 134(a).
Representative independent claim 1 is reproduced below:
1. A heterogeneous computer system
comprising:
a plurality of interconnected cells, each of the cells further
comprising:
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at least one primary processor,
a memory, and
at least one type register readable by at least one processor
selected from the group consisting of the primary
processor and an optional management processor of the
cell, the type register containing instruction set
architecture type information associated with the primary
processor of the cell;
wherein the primary processor of a first cell is of a first
Instruction Set Architecture type, and the primary
processor of a second cell is of a second Instruction set
architecture type;
wherein the system is capable of being partitioned into a
plurality of partitions, wherein each partition comprises
at least one said primary processor and is capable of
executing an operating system; and
wherein the system further comprises firmware capable of using
information in the type register of each of the plurality of
cells during system startup to ensure that all said primary
processors of each of the plurality of partitions have
compatible Instruction set architecture types.

The following reference is relied on by the Examiner:
Smith US 6,289,391 B1 Sep. 11, 2001
Claims 1 through 20 stand rejected under 35 U.S.C. § 102(b) as being
anticipated by Smith.
Rather than repeat the positions of the Appellant and the Examiner,
reference is made to the Brief for Appellant’s positions, and to the Answer
for the Examiner’s positions.
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OPINION
Generally for the reasons set forth by the Examiner in the Answer, we
sustain the rejection of all the claims on appeal under 35 U.S.C. § 102. In
the Brief, we will treat independent claim 1 as representative of the
collective arguments apparently made with respect to independent claims 1,
7, and 16, but we will consider independent claim 20 separately because it
has been argued separately. Additional arguments have been presented only
as to dependent claims 2 and 10.
Page 13 of the disclosed invention sets forth the Abstract of the
invention which indicates that each cell of a heterogeneous computer system
may have multiple primary processors of the same Instruction Set
Architecture (ISA), but some cells may be different in that they would have
different ISA types. Beginning with Appellant’s consideration of the prior
art at the Specification at page 1, the discussion indicates that multiple
primary processors may have multiple instruction set types but does not
specifically recite that they may be different. Correspondingly, the
discussion at Specification page 2 generally indicates that multiple primary
processors may have multiple operating systems of different types. In
contrast, the subject matter of the independent claims on appeal merely
recites that the first cell may have a first instruction set type architecture
whereas the second cell is stated to cite a second instruction set architecture
type. These claims do not require that the first and second instruction set
types be different from each other.
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Paragraph 4 of the prior art discussion at Specification page 1
indicates that prior art system management processors were known to exist
which is also confirmed at paragraph 7 at Specification, page 2. These are
considered different physical processor management types to the extent
recited in dependent claim 2 argued before us. Moreover, the field
replaceable capability of prior art cells discussed in paragraph 7 indicates the
art recognizes that the field programmable gate array type of architecture
argued before us in dependent claim 10 was also known in the art.
At the bottom of page 9 of the Answer where the Examiner responds
to Appellant’s arguments in the Brief, the Examiner refers to Appellant’s
arguments beginning at page 5 through 8 of the Brief alleging that Smith
fails to disclose “boot-time rendezvous and partitioning of a computer
system heterogeneous at the instruction set architecture level.” The
Examiner appears to agree with this observation but also further adds that
the claims do not recite this feature. Representative independent claim 1, for
example, merely recites operations at system startup. This is not necessarily
per se boot-time partitioning to the extent argued in the noted pages in the
Brief. Even so, it is further noted that paragraph 10 at Specification, page 2,
indicates that compatibility determinations were made in the prior art at
system boot-time even at the operating system level. Therefore, Appellant’s
arguments are not well taken, including the observation that Smith merely
operates at different operating system levels rather than at boot-time levels.

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The rule that anticipation requires that every element of a claim
appears in a single reference accommodates situations where the common
knowledge of “technologies” is not recorded in a reference, i.e., where
technical facts are known to those in the field of the invention. Continental
Can Co. v. Monsanto Co., 948 F.2d 1264, 1269 (Fed. Cir. 1991). Similarly,
In re Graves, 69 F.3d 1147, 1152 (Fed. Cir. 1995) confirms the longstanding
interpretation that the teachings of a reference may be taken in combination
with knowledge of the skilled artisan to put the artisan in possession of the
claimed invention within 35 U.S.C. § 102 even though the patent does not
specifically disclose certain features.
As to Smith, even the title of this patent indicates that it relates to a
heterogeneous computer environment. The Abstract plainly indicates the
interrelationships between a first and second operating system, labeled client
and server operating systems, for conversion between operating systems for
compatibility purposes between them. The Field of Invention discussion at
the bottom of column 1 of Smith plainly indicates that this heterogeneous
computer system of Smith operates to determine compatibility between two
different operating systems. This is also buttressed in the prior art
discussion of Figure 1 at column 4 and particularly the teachings at lines 52
through 63 of this column, in addition to the showings of the different
instruction set architectures in Figure 2 and the discussion beginning at the
middle of column 5 relative to this figure. The discussion at this column in
the paragraph beginning at line 53 emphasizes that different computer
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structures and different operating systems with different instruction set
architectures are taught.
Turning to the subject matter of dependent claim 2 argued briefly at
page 7 of the Brief, we agree with the Examiner’s approach to correlate
Smith’s IDL compiler in Figure 2 to the claimed feature, since such a
compiler must necessarily be embodied in a physical processor to the extent
a physical processor is recited in dependent claim 2. Note as well our
assessment of the prior art in the Specification earlier in this opinion. With
respect to compiler 102 in Smith, the separate server and client compilers
105 and 110 are also shown at Figure 2. Compilers necessarily operate at
the instruction set level. We also agree with the Examiner’s observation that
page 10 of the Answer that the extent of Appellant’s arguments with respect
to claim 2 is not actually claimed.
As to dependent claim 10, the Examiner takes the initial view at
page 6 of the Answer that the claimed field programmable gate array
(FPGA) is taught at column 3, lines 29 and 30. Although we regard this as a
weak basis for this feature, we are mindful that Appellant’s recognition of
the prior art field programmable cells already noted earlier in this opinion in
the prior art. Moreover, Appellant’s discussion of claim 10 at the top of
page 8 of the Brief recognizes that FPGAs were well known in the art as
structural elements of large integrated circuit structures with correlated
teachings associated with EEPROMs or EPROMs. The Examiner’s remarks
in the paragraph bridging pages 10 and 11 of the Answer are also persuasive
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since the Examiner recognizes that FPGAs are also well-known in the art
and by definition may be programmed after manufacture. It is further noted
that the bulk of the figures in Smith already indicate that various register-to-
register communications occur between the various processors embodying
the different operating systems and different instruction sets to the extent
generally recited in each independent claim on appeal.
Lastly, we turn to the positions set forth at page 8 of the Brief relative
to independent claim 20 to which the Examiner responds at page 11 of the
Answer. We generally agree with the Examiner’s position that Appellant’s
arguments are not commensurate with the scope of the claim. Moreover, our
earlier remarks in this opinion appear to address the substance of the
arguments at page 8 of the Brief anyway because it is known in the art
according to Appellant’s own recognition that the same or different
operating systems in the same or different instruction set architectures may
be embodied in the same heterogeneous computer system, notwithstanding
the intent of Smith to have them be different. The whole focus of Smith is to
determine the compatibility between different operating systems and
instruction set architecture types as best expressed at the end of the Abstract
of Smith’s patent.
These compatibility determinations also take an interesting twist in
view of the generalized teachings at column 12, line 66 through column 13,
line 32 indicating the interchangeability of the disclosed first and second
operating systems in Smith.
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As a closing matter, we have not considered any of the remarks set
forth in the Reply Brief since they are not essentially responsive to the
Examiner’s responsive arguments set forth in the Answer and are not truly a
reply to the Answer. The substance of the remarks in the Reply Brief
actually appears to be new arguments of the nature that should have been
presented in the principal Brief on appeal. The stated rejection in the
Answer is the same as that set forth in the final rejection. The positions set
forth in the Reply Brief are considered to have been waived because they
were not raised in Appellant’s opening Brief. See Optivus Tech., Inc. v. Ion
Beam Applications S.A., 469 F.3d 978, 989, 80 USPQ2d 1839, 1847-48
(Fed. Cir. 2006).
In view of the foregoing, the decision of the Examiner rejecting all
claims on appeal under 35 U.S.C. § 102 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).
AFFIRMED

clj

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