Ex Parte Merk

Board of Patent Appeals and Interferences

Feb 25, 2010

11095283 (B.P.A.I. Feb. 25, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte DIETER MERK
____________________

Appeal 2009-000052
Application 11/095,2831
Technology Center 2100
____________________

Decided: February 25, 2010
____________________

Before JAMES D. THOMAS, JEAN R. HOMERE, and JAMES R.
HUGHES, Administrative Patent Judges.

HUGHES, Administrative Patent Judge.

DECISION ON APPEAL

1 Application filed March 31, 2005. The application claims foreign priority
under 35 U.S.C. § 119(a-d) to German patent application No. 10 2004
016367.1 filed April 2, 2004. The real party in interest is Texas Instruments,
Inc. (Br. 2.)
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STATEMENT OF THE CASE
Appellant appeals the Examiner’s rejection of claims 1-5, 7, and 8
under 35 U.S.C. § 134(a). The Examiner allowed claim 9, and indicated that
claim 6 is allowable but objected to as being dependent on a rejected base
claim. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

Appellant’s Invention
Appellant invented an interface circuit (apparatus) utilizing a single
input pin to selectively switch an electronic system into a test mode. The
interface circuit includes a decoder for converting a pulse coded signal
applied to the input pin into a sequence of logic low and logic high values,
and a state machine responsive to the sequence of logic values to switch the
electronic system between different modes of operation. (Spec. 4, ll. 5-15.)2

Representative Claim
Independent claim 1 further illustrates the invention. It reads as
follows:
1. An interface circuit for a single logic input pin of an
electronic system, comprising
a decoder for converting a pulse coded signal applied to
said pin to a sequence of logic low and logic high values, and
a state machine with at least three states and responsive
to said sequence of logic values to switch the electronic system
between different modes of operation.

2 We refer to Appellant’s Specification (“Spec.”) and Appeal Brief (“Br.”)
filed July 30, 2007. We also refer to the Examiner’s Answer (“Ans.”)
mailed September 27, 2007.
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References
The Examiner relies on the following reference as evidence of
unpatentability:
Meli US 6,657,451 B2 Dec. 2, 2003

Kimelman US 2004/0210805 A1 Oct. 21, 2004
(filed Apr. 17, 2003)

Kotowski US 6,888,765 B1 May 3, 2005
(filed Feb. 4, 2002)

Rejections
The Examiner rejects claims 1-5 and 7 under 35 U.S.C. § 103(a) as
being unpatentable over the combination of Meli and Kimelman.
The Examiner rejects claim 8 under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Meli, Kimelman, and Kotowski.

Appellant’s Contentions
Appellant contends that “[b]ase claim 1 requires a single-pin interface
with a decoder plus a state machine with at least three states,” and the
combination of Meli and Kimelman “does not suggest any interface state
machine with at least three states.” (App. Br. 3.)

Examiner’s Findings and Conclusions
The Examiner finds that the prior art teaches each feature of
Appellant’s claims (Ans. 3-4), and maintains that each of the claims is
properly rejected (Ans. 5-6). In particular, the Examiner finds that Meli
teaches an interface including a single logic input pin receiving a pulse
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coded signal and a decoder converting the pulse coded signal into logical
high and low values. (Ans. 4.) The Examiner also finds that Kimelman
teaches an interface circuit which “exhibits at least three states . . . and is
responsive to a sequence of logic values to switch the electronic system
between different modes of operation.” (Ans. 4.)

ISSUE
Based on Appellant’s contentions, as well as the findings and
conclusions of the Examiner, the pivotal issue before us is as follows.
Does Appellant establish that the Examiner erred in finding the Meli
and Kimelman references collectively teach or would have suggested a
single-pin interface with a decoder plus a state machine with at least three
states?

FINDINGS OF FACT (FF)
Appellant’s Admissions
1. Appellant explicitly states that “Meli shows a single pin
decoder.” (Br. 3.)
2. Appellant explicitly states that Kimelman “relates to the single-
pin communication protocol . . . which includes the interface 6” and “four
protocol modes/states.” (Br. 3-4.)

Meli Reference
3. Meli describes a system and method switching an integrated
circuit into a test mode utilizing a single pin. (Col. 1, ll. 8-12, 40-48.) Meli
describes an integrated circuit, i.e., an interface circuit, including a single
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test pin for receiving a pulse coded signal and a decoder for converting the
pulse coded signal into logical high and low values for switching an
integrated circuit into a test mode. (Col. 1, l. 66 to col. 2, l. 7; Figs. 1, 3,
elements 20, 22, 26, 28, 36, 40.)

Kimelman Reference
4. Kimelman describes an integrated circuit including an interface
circuit and a diagnostic circuit utilizing a serial link (single pin) that receives
a serial communications protocol, which switches the integrated circuit into
a number of different modes or states including a data (test) mode.
(Abstract; ¶¶ [0002]-[0004], [0058]-[0061].) The integrated circuit responds
to the serial communication protocol, and switches among reset, training,
data, and idle states. (¶¶ [0047]-[0054], [0077]-[0089]; Fig. 1.)

PRINCIPLES OF LAW
Prima Facie Case of Unpatentability
The allocation of burden requires that the United States Patent and
Trademark Office (USPTO) produce the factual basis for its rejection of an
application under 35 U.S.C. § 103. In re Piasecki, 745 F.2d 1468, 1472
(Fed. Cir. 1984) (citing In re Warner, 379 F.2d 1011, 1016 (CCPA 1967)).
The Examiner bears the initial burden of presenting a prima facie case of
unpatentability. In re Oetiker, 977 F.2d 1443, 1445 (Fed. Cir. 1992). An
Appellant has the opportunity on appeal to the Board of Patent Appeals and
Interferences (BPAI) to demonstrate error in the Examiner’s position. See In
re Kahn, 441 F.3d 977, 985-86 (Fed. Cir. 2006) (“[o]n appeal to the Board,
an applicant can overcome a rejection by showing insufficient evidence of
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prima facie obviousness or by rebutting the prima facie case with evidence
of secondary indicia of nonobviousness.”) (quoting In re Rouffet, 149 F.3d
1350, 1355 (Fed. Cir. 1998)).

Obviousness
A claimed invention is not patentable if the subject matter of the
claimed invention would have been obvious to a person having ordinary skill
in the art. 35 U.S.C. § 103(a); KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398,
406 (2007); Graham v. John Deere Co., 383 U.S. 1, 13 (1966). The
question of obviousness is resolved on the basis of underlying factual
determinations including (1) the scope and content of the prior art, (2) any
differences between the claimed subject matter and the prior art, (3) the level
of skill in the art. Graham, 383 U.S. at 17. See also KSR, 550 U.S. at 407
(“While the sequence of these questions might be reordered in any particular
case, the [Graham] factors continue to define the inquiry that controls.”)
In KSR, the Supreme Court emphasizes “the need for caution in
granting a patent based on the combination of elements found in the prior
art,” and stated that “[t]he combination of familiar elements according to
known methods is likely to be obvious when it does no more than yield
predictable results.” KSR, 550 U.S. at 415-16. The Court explained:
When a work is available in one field of endeavor, design
incentives and other market forces can prompt variations of it,
either in the same field or a different one. If a person of
ordinary skill can implement a predictable variation, § 103
likely bars its patentability. For the same reason, if a technique
has been used to improve one device, and a person of ordinary
skill in the art would recognize that it would improve similar
devices in the same way, using the technique is obvious unless
its actual application is beyond his or her skill.
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Id. at 417. The operative question is thus “whether the improvement is more
than the predictable use of prior art elements according to their established
functions.” Id.

ANALYSIS
Based on Appellant’s arguments in the Appeal Brief, we choose
Appellant’s independent claim 1 as representative. Appellant does not
separately argue dependent claims 2-5, 7, and 8. (Br. 3-4.) We address only
those arguments that Appellant presents in the Brief. Arguments that
Appellant could have made but chose not to make in the Brief are waived.
See 37 C.F.R. § 41.37(c)(1)(vii) (“Notwithstanding any other provision of
this paragraph, the failure of appellant to separately argue claims which
appellant has grouped together shall constitute a waiver of any argument that
the Board must consider the patentability of any grouped claim separately.”).
Appellant’s sole argument on appeal is that the combination of the
Meli and Kimelman references does not teach a state machine with at least
three states. (Br. 3-4.) Appellant concedes that Meli teaches a single-pin
interface with a decoder – “Meli shows a single pin decoder.” (FF 1.)
Appellant further concedes that Kimelman teaches a single pin interface and
serial communication protocol that switches an integrated circuit into four
different states. (FF 2.)
Meli describes an interface circuit including a single test pin for
receiving a pulse coded signal and a decoder for converting the pulse coded
signal into logical high and low values for switching an integrated circuit
into a test mode. (FF 3.) Similarly, Kimelman describes an integrated
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circuit with an interface utilizing single-pin serial link that receives a serial
communications protocol, which switches the integrated circuit into a
number of different modes or states including a reset, training, data, and/or
idle mode/state. (FF 4.) Thus, we find that an ordinarily-skilled artisan
would have understood the combination of Meli and Kimelman to describe
an interface circuit including a single test pin for receiving a pulse coded
signal and a decoder for converting the pulse coded signal into logical high
and low values for switching an integrated circuit into a number of different
modes or states including a reset, training, data (test), and/or idle mode/state.
Appellant’s, argument, then, boils down to whether the Meli and
Kimelman references teach “a state machine.” We determine the scope of
the claims in patent applications not solely based on the claim language, but
upon giving claims “their broadest reasonable interpretation consistent with
the [S]pecification” and “in light of the [S]pecification as it would be
interpreted by one of ordinary skill in the art.” In re Am. Acad. of Sci. Tech
Ctr., 367 F.3d 1359, 1364 (Fed. Cir. 2004) (citations omitted). Appellant
does not explicitly define a “state machine,” but does explain that a “[s]tate
machine 12 assumes different states in accordance with predetermined
patterns of logic low and logic high values. In each of the different states,
state machine 12 provides a different command on its outputs.” (Spec. 6, ll.
19-21.) Appellant further explains that:
The interface circuit also includes a state machine responsive
to the sequence of logic values to switch the electronic system
between different modes of operation. Depending on the
selected mode of operation, the single input pin will function
as one out of several separate (logic) input channels.
Accordingly, the single input pin of a small electronic system
can be used in multiple ways. Since the pulse coded signal
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may define an unlimited number of different logic high/low
sequences, i.e. bit patterns, each corresponding to a particular
state of the state machine, the number of uses for the single
input pin is virtually infinite.
(Spec. 4, ll. 8-15.)
Thus, we interpret a “state machine” to mean a device (e.g., a circuit
and/or a computer implementing software) that switches an integrated circuit
into different modes or states of operation. This definition is consistent with
the common definition of a “state machine” as would be recognized by one
of skill in the art – “A model of computation consisting of a (possibly
infinite) set of states, a set of start states, an input alphabet, and a transition
function which maps input symbols and current states to a next state.”
Dictionary of Algorithms and Data Structures, Paul E. Black, ed., U.S.
National Institute of Standards and Technology (December 12, 2005),
available from:
http://www.itl.nist.gov/div897/sqg/dads/HTML/statemachine.html, last
visited February 22, 2010. Accordingly, we broadly but reasonable interpret
the disputed limitation to mean a device that switches an integrated circuit
into at least three different modes or states of operation.
After reviewing the record on appeal, we find the combination of the
Meli and Kimelman references collectively teaches or would have suggested
the disputed limitation. Specifically, we find that although Kimelman does
not explicitly mention “a state machine,” Kimelman does teach a device that
switches an integrated circuit into at least three different modes or states of
operation. We agree with the Examiner that Meli teaches each of the recited
features except a state machine with at least three states, and we find
Kimelman teaches or would have suggested this feature. (See FF 4). We are
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not persuaded by Appellant’s contrary arguments that the Meli-Kimelman
combination does not teach a device that switches an integrated circuit into
at least three different modes or states of operation – i.e., a state machine
with at least three states. For the foregoing reasons, Appellant has not
persuaded us of error in the Examiner’s obviousness rejections of claims 1-
5, 7, and 8. Accordingly, we affirm the Examiner’s rejections of these
claims.

CONCLUSION OF LAW
On the record before us, we find that Appellant has not established
that the Examiner erred in finding the Meli and Kimelman references
collectively teach or would have suggested a single-pin interface with a
decoder plus a state machine with at least three states.

DECISION
We affirm the Examiner’s rejections of claims 1-5, 7, and 8 under
35 U.S.C. § 103(a).

No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

rwk/nhl

Texas Instruments Incorporated
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