Ex Parte Mejdrich et al

Patent Trial and Appeal Board

May 20, 2013

11536146 (P.T.A.B. May. 20, 2013)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/536,146 09/28/2006 Eric Oliver Mejdrich ROC920060116US1 8589
46797 7590 05/21/2013
IBM CORPORATION, INTELLECTUAL PROPERTY LAW
DEPT 917, BLDG. 006-1
3605 HIGHWAY 52 NORTH
ROCHESTER, MN 55901-7829
EXAMINER
BADER, ROBERT N.
ART UNIT PAPER NUMBER
2679
MAIL DATE DELIVERY MODE
05/21/2013 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte ERIC OLIVER MEJDRICH, ADAM JAMES MUFF,
and MATTHEW RAY TUBBS
____________________

Appeal 2010-012342
Application 11/536,1461
Technology Center 2600
____________________

Before MARC S. HOFF, DAVID M. KOHUT, and
PATRICK M. BOUCHER, Administrative Patent Judges.

BOUCHER, Administrative Patent Judge.

DECISION ON APPEAL

1 The real party in interest is International Business Machines Corporation.
Appeal 2010-012342
Application 11/536,146
2
STATEMENT OF THE CASE
Introduction
Appellants appeal under 35 U.S.C. § 134 from a rejection of claims 1,
3–10, 12, 14–16, and 18–24.2 We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

Illustrative Claim
The disclosure relates to vector units for supporting image processing
(Abs.). The claims are directed to a dual vector unit that may access the
same register file and that include a plurality of vector processing lanes and
that may include a scalar processing lane to integrate the processing of
vector and scalar instructions (Spec. ¶90).
Claim 1 is illustrative and is reproduced below with the disputed
limitation emphasized:
1. A processor, comprising:
a first vector unit; and
a second vector unit,
wherein the first vector unit and the second vector unit
each comprise a plurality of vector processing lanes configured
to execute a vector instruction and at least one scalar processing
lane configured to execute a scalar instruction, the first vector
unit and the second vector unit being configured to
independently and simultaneously execute instructions, and
wherein the first vector unit and the second vector unit
are configured to execute a single vector instruction in the
plurality of vector processing lanes of the first vector unit, the
at least one scalar processing lane of the first vector unit, and
one or more of the plurality of vector processing lanes of the
second vector unit.

2 Claims 2, 11, 13 and 17 have been canceled.
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References
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Yoshida US 4,685,076 Aug. 4, 1987
Maher US 2005/0251644 A1 Nov. 10, 2005

M. A. S. Dal Poz, B. B. Gnecco, M. K. Zuffo, “A High Performance
Processor for Real-Time Ray-Tracing Image Rendering,” 48th Midwest
Symposium on Circuits and Systems (IEEE, 2005), pp. 867–870.

Rejections
The Examiner made the following rejections:
Claims 1, 4–10, 14–16, and 19–24 stand rejected under 35 U.S.C
§103(a) as unpatentable over Maher in view of Yoshida (Ans. 3).
Claims 3, 12, and 18 stand rejected under 35 U.S.C §103(a) as
unpatentable over Maher in view of Yoshida, and further in view of Dal Poz
(Ans. 13–14).
Throughout this decision, we reference the Appeal Brief (“Br.,” filed
May 20, 2010) and the Examiner’s Answer (“Ans.,” dated June 8, 2010) for
their respective details.

Issue
Appellants argue that the vector units of Yoshida do not teach a
plurality of vector processing lanes and that Maher and Yoshida are
incompatible (Br. 10–13). The Examiner finds that all limitations of the
independent claims are taught by Maher, including execution of a single
vector instruction in the plurality of vector processing lanes of the first
vector unit and the at least one scalar processing lane of the first vector unit
(Ans. 4–5). The Examiner relies on Yoshida’s disclosure of dividing a
Appeal 2010-012342
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single vector instruction in multiple vector units in finding it obvious over
the cited art for execution of the single vector instruction also to involve one
or more of the plurality of vector processing lanes of the second vector unit
(Ans. 5–6).
Appellants’ contentions and the Examiner’s findings present us with
the following issue:
Is the limitation,
wherein the first vector unit and the second vector unit are
configured to execute a single vector instruction in the plurality
of vector processing lanes of the first vector unit, the at least one
scalar processing lane of the first vector unit, and one or more of
the plurality of vector processing lanes of the second vector unit

obvious over the combined disclosures of Maher and Yoshida?

ANALYSIS
Principles of Law
35 U.S.C. § 103(a) forbids issuance of a patent when “the differences
between the subject matter sought to be patented and the prior art are such
that the subject matter as a whole would have been obvious at the time the
invention was made to a person having ordinary skill in the art to which said
subject matter pertains.” KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 406
(2007). The question of obviousness is resolved on the basis of underlying
factual determinations that include (1) the scope and content of the prior art,
(2) any differences between the claimed subject matter and the prior art, (3)
the level of skill in the art, and (4) secondary considerations. Graham v.
John Deere Co., 383 U.S. 1, 17–18 (1966). See also KSR, 550 U.S. at 407
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(“While the sequence of these questions might be reordered in any particular
case, the [Graham] factors continue to define the inquiry that controls”).

Claim 13
Appellants’ argument based on their assertion that “the vector units of
Yoshida do not each include a plurality of vector processing lanes” (Br. 11)
is unpersuasive. This argument attacks Yoshida individually for lack of a
teaching where the Examiner has, in fact, relied on the combination of
references for the relevant teaching. The test for obviousness is what the
combined teachings of the prior art would have suggested to the hypothetical
person of ordinary skill in the art. In re Keller, 642 F.2d 413, 425 (CCPA
1981).
As the Examiner correctly observes, Yoshida explicitly suggests
multiple processing lanes in multiple processing units and provides a pattern
for dividing multiple vector elements among multiple vector processing
units (Ans. 15). These disclosures would reasonably commend themselves
to one of skill in the art in understanding that Maher may be modified to
apply the instruction-dividing technique taught by Yoshida.
Appellants’ contentions that Maher and Yoshida are incompatible
misapplies the Examiner’s basis for rejection. Contrary to Appellants’
characterization, the Examiner does not propose “modifying Maher to
include the vector units of Yoshida” (Br. 11). Rather, the Examiner

3 Appellants argue claims 1, 4–10, 14–16, and 19–24 collectively. While
claims 3, 12, and 18 are presented under a separate heading, no additional
arguments are presented to establish separate patentability. We therefore
treat claim 1 as representative of all claims. See 37 C.F.R.
§ 41.37(c)(1)(vii). Except for our ultimate decision, the other claims are not
discussed further herein.
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articulates a modification that applies Yoshida’s technique of dividing one
instruction among multiple processors (Ans. 16), and does not rely on
adding Yoshida’s structure to Maher’s structure.
Since we find Appellants’ arguments unpersuasive, we sustain the
Examiner’s rejection.

CONCLUSION
On the record before us, we conclude that the Examiner did not err in
finding that the combination of Maher and Yoshida reasonably suggest:

wherein the first vector unit and the second vector unit are
configured to execute a single vector instruction in the plurality
of vector processing lanes of the first vector unit, the at least one
scalar processing lane of the first vector unit, and one or more of
the plurality of vector processing lanes of the second vector unit.

We therefore conclude that the Examiner has not erred in rejecting
claims 1, 3–10, 12, 14–16, and 18–24 under 35 U.S.C. § 103(a).

DECISION
The Examiner’s decision rejecting claims 1, 3–10, 12, 14–16, and 18–
24 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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