Ex Parte Meir et al

Board of Patent Appeals and Interferences

Jun 25, 2010

11159172 (B.P.A.I. Jun. 25, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
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Ex parte AVRAHAM MEIR and AMIR RONEN
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Appeal 2009-002100
Application 11/159,172
Technology Center 2100
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Decided: June 25, 2010
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Before JAMES D. THOMAS, CAROLYN D. THOMAS, and
STEPHEN C. SIU, Administrative Patent Judges.

C. THOMAS, Administrative Patent Judge.

DECISION ON APPEAL
Appeal 2009-002100
Application 11/159,172

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STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) from a final rejection of
claims 1-3 and 5-12. Claim 4 is cancelled and claims 13-15 are allowed
(App. Br. 7). We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.

According to Appellants, the invention relates to a method of
accessing a memory, such as a flash memory, "as though the physical size of
an erase block were smaller than it really is" (Spec. 1, ll. 13-15).

Claim 1 is illustrative:
1. A method of managing a memory, comprising the
steps of:
(a) structuring the memory as a plurality of physical
blocks having a certain size, the memory being erased in units
of said physical blocks;
and
(b) presenting the memory as though the memory is
erased in units of pseudo-blocks that are smaller in size than
said physical blocks.

Rejections
Claims 1-3 and 5-12 stand rejected 35 U.S.C. § 103(a) as being
unpatentable over Rocchi (US 6,581,134 B2, June 17, 2003) and Matthews
(US 5,860,124, Jan. 12, 1999).

Appeal 2009-002100
Application 11/159,172

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GROUPING OF CLAIMS
(1) Appellants argue claims 1-3 and 5-12 as a group on the basis of
independent claims 1, 10, and 12 (App. Br. 12). We select independent
claim 1 as the representative claim. See 37 C.F.R. § 41.37(c)(1)(vii). We
will, therefore, treat claims 2, 3 and 5-12 as standing or falling with
representative claim 1.

FINDINGS OF FACT (FF)
Rocchi Reference
1a. Rocchi discloses: "A further problem of managing physical
sectors of large dimensions is eliminating only a small amount of data in a
sector while retaining the remaining data. This is problematic because in
FLASH memories[,] it is possible only to erase a whole physical sector and
not just a portion of it." (Col. 1, ll. 34-38).
1b. Rocchi discloses: "Because of this memory organization, the
memory does not appear to the user as including physical sectors of large
dimensions. Rather, it appears to have logic sectors of relatively small
dimensions that are individually addressable and whose contents can be
updated independently from the other logic sectors." (Col. 2, ll. 46-51).
1c. Rocchi discloses: "As previously stated, the commonly used
technique for erasing a portion of a physical sector includes using a
BUFFER sector unaccessible by the user. Before erasing a physical sector,
the data to be saved is temporarily saved in this prearranged buffer space.
Once the sector is erased, the saved data is copied back into the erased
sector." (Col. 4, ll. 48-52).
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Matthews Reference
2. Matthews discloses: Figure 6 illustrates block 610. Logical
sector numbers 8, 5, and 63 are within the first block 610. (See col. 9, ll. 8-
14; see also FIG. 6).
PRINCIPLES OF LAW
Obviousness
In rejecting claims under 35 U.S.C. § 103, it is incumbent upon the
Examiner to establish a factual basis to support the legal conclusion of
obviousness. See In re Fine, 837 F.2d 1071, 1073 (Fed. Cir. 1988). If the
Examiner's burden is met, the burden then shifts to the Appellants to
overcome the prima facie case with argument and/or evidence. Obviousness
is then determined on the basis of the evidence as a whole and the relative
persuasiveness of the arguments. See In re Oetiker, 977 F.2d 1443, 1445
(Fed. Cir. 1992).

ANALYSIS
Claims 1-3 and 5-12
Issue 1: Did the Examiner err in finding the prior art teaches or
suggests "presenting the memory as though the memory is erased in units of
pseudo-blocks that are smaller in size than said physical blocks," as recited
in claim 1?
Appellants assert "[n]either prior art document . . . teaches . . .
presenting the memory as though the memory is erased in units of pseudo-
blocks that are smaller in size than the physical blocks," as recited in
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independent claims 1, 10, and 12, as (1) the Examiner concedes that this
feature is not taught in Rocchi reference (App. Br. 12) and (2) the Matthews
reference presents its solid state disk to its host as an electromechanical hard
drive that "does not need to be erased before being written over" (App. Br.
13).
Further, Appellants argue "[p]seudo-blocks" are defined in Appellants'
Specification in terms of erasure and Matthews "does not present its
nonvolatile semiconductor memory as being erased in any kind of blocks"
(App. Br. 14).
The Examiner finds that "Rocchi clearly teaches . . . presenting the
memory as though the memory is erased in units (col. 6 - 18-29)", but does
not specifically teach presenting the memory as though the memory is erased
in units of pseudo-blocks that are smaller in size than the physical blocks
(Ans. 7). The Examiner further finds that Matthews teaches (1) a first block
610, as shown in Figure 6 (id. at 7) and (2) logical sectors 611, 613, 616, and
617 that are part of the entire first block 610, and thus, "can be interpreted as
pseudo-blocks, which [are] units of smaller groups in the entire first block”
(Ans. 8). We agree in part with the Examiner.
For example, Rocchi clearly teaches erasing a physical sector
(FFs. 1a and 1c). However, contrary to the Examiner’s findings, we also
find that Rocchi gives the illusion of erasing a smaller portion of a physical
sector (FF. 1c). For instance, before erasing a physical sector in Rocci, the
data to be saved is temporarily saved in a prearranged buffer space. Once
the sector is erased, the saved data is copied back into the erased sector.
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Hence, Rocci presents the memory as though the memory is erased in units
of pseudo-blocks that are smaller in size than said physical blocks.
Further, we find it would have been obvious to one of ordinary skill in
the art that a physical sector of Rocchi corresponds to the physical block of
claim 1, and a portion of Rocchi's physical block corresponds to a pseudo-
block of claim 1, as a portion of a physical sector clearly suggests a unit of a
physical sector that is smaller than the whole physical sector (i.e., physical
block). Thus, we find Rocchi teaches blocks of two different sizes, i.e.,
(1) physical sectors (corresponding to physical blocks) and (2) portions of
physical sectors (corresponding to pseudo-blocks). Similarly, Matthews
discloses that it was known to manipulate smaller sectors of a physical
memory block (FF. 2.)
Accordingly, we find that the combination of Rocchi and Matthews
teaches or suggests "presenting the memory as though the memory is erased
in units of pseudo-blocks that are smaller in size than said physical blocks,"
as recited in claim 1.

Issue 2: Did the Examiner err in combining Rocchi and Matthews?

ANALYSIS
Appellants argue "[i]t would be improper to combine the teachings of
Rocchi and Matthews under the assumption that Rocchi's 'sectors'
correspond to Matthews' 'sectors,'" as what Rocchi and Matthews mean by a
"sector" are two entirely different things (App. Br. 15). Appellants contend
(1) "[t]he portion of a flash memory that Rocchi calls a 'sector' is usually
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referred to in the art as a 'block'" and (2) "what Matthews means by a 'sector'
is what the above-identified patent application refers to as the smallest group
of memory cells that can be written collectively” (App. Br. 15).
The Examiner finds "the test for obviousness is not whether the
features of a secondary reference may be bodily incorporated into the
structure of the primary reference; nor is it that the claimed invention must
be expressly suggested in any one or all of the references," but "the test is
what the combined teachings of the references would have suggested to
those of ordinary skill in the art" (Ans. 9). We again agree with the
Examiner.
We further add that Rocci discloses all of the disputed features (i.e.,
presenting the memory as though the memory is erased in units of
pseudo-blocks that are smaller in size than said physical blocks) and
Matthews' teachings are merely cumulative to showing the use of pseudo-
blocks. Thus, we find Appellants' arguments that there is no motivation to
combine Rocchi and Matthews as moot, as the Matthews reference is only
cumulative.
Even if Matthews was not cumulative, which it is, in analyzing
whether it would have been obvious to one of ordinary skill in the art to
make a modification or combination, there does not have to be an express
teaching, suggestion, or motivation (TSM) in a published article or issued
patent. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 419 (2007) ("The
obviousness analysis cannot be confined by a formalistic conception of the
words teaching, suggestion, and motivation, or by overemphasis on the
importance of published articles and the explicit content of issued patents.").
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The test for obviousness is what the combined teachings of the references
would have suggested to the artisan. Here, the Examiner has shown that the
combined teachings would have suggested presenting the memory as though
the memory is erased in units of pseudo-blocks that are smaller in size than
said physical blocks.
Accordingly, we find the Examiner did not err in combining the
Rocchi and Matthews references. Thus, for all of the reasons discussed
above, we find the Examiner did not err in rejecting claim 1 under 35 U.S.C.
§ 103, and claims 2, 3 and 5-12, which fall therewith.

DECISION
We affirm the Examiner's rejection of claims 1-3 and 5-12 under
35 U.S.C. § 103(a).
No time period taking any subsequent action in connection with this
appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv) (2009).

AFFIRMED

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