Ex Parte McKinnell

Board of Patent Appeals and Interferences

Jan 31, 2007

10029649 (B.P.A.I. Jan. 31, 2007)

The opinion in support of the decision being entered today was not
written for publication and is not binding precedent of the Board.

UNITED STATES PATENT AND TRADEMARK OFFICE
__________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
__________

Ex parte JAMES C. MCKINNELL
__________

Appeal No. 2006-2218
Application No. 10/029,649
___________

ON BRIEF
___________

Before BARRY, BLANKENSHIP, and SAADAT, Administrative Patent
Judges.

SAADAT, Administrative Patent Judge.

DECISION ON APPEAL

This is a decision on appeal under 35 U.S.C. § 134(a) from
the Examiner’s final rejection of claims 1-4, 6-11, 14-17, 33 and
34. Claims 5, 12 and 13 have been canceled and claims 18-32 and
35-39 have been withdrawn from consideration as being drawn to a
non-elected invention.
We affirm.
Appeal No. 2006-2218
Application No. 10/029,649

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BACKGROUND
Appellant’s invention is directed to a method of bonding
semiconductor substrates or wafers with a bonding material that
includes an oxide affinity material. According to Appellant,
instead of the conventional ways of removing the unwanted native
oxide, which is formed on the exposed surface of the wafer, a
reducing agent included in the bonding material removes the
native oxide from the interface (Specification, 3). An
understanding of the invention can be derived from a reading of
exemplary independent claim 1, which is reproduced below:
1. An electrical device comprising:
first and second substrates having respective first and
second integrated circuits, wherein at least one of the first
substrate or the second substrate has a semiconductor layer
thereon; and

a bond structure bonding the first substrate to the second
substrate, the bond structure including an alloy:

bonded to the semiconductor layer;
composed of noble metal alloyed with an oxide affinity
material having an affinity for oxygen higher than that of
the material of which the semiconductor layer is composed
such that the alloy is sufficient to remove a native oxide
from an interface surface between the bond structure and the
first substrate; and

configured to form an electrical connection between the
first integrated circuit and the second integrated circuit.

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Application No. 10/029,649

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The Examiner relies on the following prior art references:
Ohara US 5,668,033 Sep. 16, 1997

Terasawa US 5,702,962 Dec. 30, 1997

Merchant US 6,118,181 Sep. 12, 2000
Claims 1, 3, 4, 6-10, 14-16, 33 and 34 stand rejected
under 35 U.S.C. § 103(a) as being unpatentable over Merchant
and Terasawa.
Claims 2, 11 and 17 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Merchant, Terasawa and
Ohara.
We refer to the briefs and answer for the respective
positions of Appellant and the Examiner. Only those arguments
actually made by Appellant have been considered in this
decision. Arguments which Appellant could have made but chose
not to make in the briefs have not been considered (37 C.F.R.
§ 41.37(c)(1)(vii)).
OPINION
With respect to the rejection of claims 1, 3, 4, 6-10,
14-16, 33 and 34, the focus of Appellant’s arguments is that the
prior art teachings do not recognize the claimed alloy properties
for oxide removal since bonding of the substrates in both
Appeal No. 2006-2218
Application No. 10/029,649

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Merchant and Terasawa are performed subsequent to removal of
native oxides from the substrates (Br. 12-15). In particular,
Appellant asserts that it is by including the recited oxide
affinity material in the amount recited that the cleaning of the
oxide, as described by the references, becomes unnecessary (Br.
15).
In response, the Examiner asserts that the cleaning step
described in Merchant is performed to clean the surface of
chromium layer 29 and has nothing to do with the bond layer 27
which is suggested to include other elements in place of or in
combination with palladium (Answer 13). The Examiner further
argues that Terasawa, while suggesting the use of acids for
removal of native oxide, does provide for an Au-Sb alloy as the
metal layer 62 at the interface of the two joining substrates
(Answer 14).
We disagree with Appellant (Br. 13) that because a cleaning
step prior to joining the substrates is suggested, the disclosed
alloy as modified by Terasawa does not remove the native oxide.
The claims require that “the alloy is sufficient to remove a
native oxide” which merely requires that the alloy have oxide
removal capability instead of actually removing the oxide.
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Application No. 10/029,649

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Merchant, on the other hand, describes cleaning of the wafer
surface prior to bonding as unnecessary (Merchant, col. 5, ll.
30-35) implying that bonding still takes place even if the
cleaning step is not performed. The bonding alloy that includes
the oxide affinity material can then remove the oxide when the
cleaning step is not performed and native oxide is present. As
argued by the Examiner (Answer 14), the metal layer 62 of
Terasawa is sufficient to remove a native oxide from the bonding
interface between the substrates since the metal layer is made of
Au-Sb alloy which has an affinity for oxygen higher than that of
silicon (Terasawa, col. 5, ll. 12-21).
We also observe that a composition ratio or the amount of
the oxide affinity material in the bond structure for the gold
alloy, as argued by Appellant (Br. 19), is not described in
Appellant’s Specification. Therefore, to the extent disclosed,
any combination ratio of Au-Sb specified by the references is
capable of removing the native oxide on the silicon substrate
interface.
Based on our analysis above, we remain unpersuaded by
Appellant’s arguments that the Examiner erred in determining the
obviousness of the claimed subject matter. Accordingly, as the
Examiner has established a prima facie case of obviousness with
Appeal No. 2006-2218
Application No. 10/029,649

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respect to claims 1, 10, 15 and 33, we sustain the 35 U.S.C.
§ 103(a) rejection of these claims, as well as dependent claims
3, 4, 6-9, 14, 16 and 34 over Merchant and Terasawa.
Turning now to the rejection of the remaining claims under
35 U.S.C. § 103 over Merchant, Terasawa and Ohara, Appellant, in
addition to the same arguments presented above with respect to
claims 1, 10 and 15, further asserts that the gold layer in Ohara
merely bonds the cap layer and cannot cure the deficiencies of
Merchant and Terasawa (Br. 25-26). We find that Ohara describes
the bonding layer between a silicon substrate and a silicon cap
layer using gold in combination with one of Ti, Al, Ta, etc.
(Ohara, col. 8, ll. 53-61) for reducing the natural oxide film on
the silicon substrate. Contrary to Appellant’s position (Br.
25), the absence of an integrated circuit in the silicon cap
layer of Ohara is irrelevant since bonding two substrates
including integrated circuits is taught by the combination of
Merchant and Terasawa, as discussed above. The Examiner relies
on Ohara for teaching the ratio of the oxide affinity material to
the interfacing gold that is taught by their respective
thicknesses (Ohara, col. 8, ll. 56-61). Accordingly, we sustain
the 35 U.S.C. § 103 rejection of claims 2, 11 and 17 over
Merchant, Terasawa and Ohara.
Appeal No. 2006-2218
Application No.10/029,649

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CONCLUSION
In view of the foregoing, the decision of the Examiner
rejecting claims 1-4, 6-11, 14-17, 33 and 34 under 35 U.S.C.
§ 103 is affirmed.
No time period for taking any subsequent action in
connection with this appeal may be extended under 37 C.F.R.
§ 1.136(a)(1)(iv).

AFFIRMED

LANCE LEONARD BARRY )
Administrative Patent Judge )
)
)
) BOARD OF PATENT
HOWARD B. BLANKENSHIP )
Administrative Patent Judge ) APPEALS AND
)
) INTERFERENCES
)
MAHSHID D. SAADAT )
Administrative Patent Judge )

MDS/ce
Appeal No. 2006-2218
Application No.10/029,649

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