Ex Parte McGregor et al

Patent Trial and Appeal Board

Dec 11, 2017

14534540 (P.T.A.B. Dec. 11, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/534,540 11/06/2014 Joel M. McGregor 164830614USC1/MAXM0825C1 1088
99900 7590 12/18/2017
Advent/Maxim
The Advent Building
17838 Burke Street
Suite 200
Omaha, NE 68118
EXAMINER
MAI, ANH D
ART UNIT PAPER NUMBER
2829
NOTIFICATION DATE DELIVERY MODE
12/18/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
u spto @ adventip .com
sloma@adventip.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte JOEL M. McGREGOR and FREDERICK P. GILES
Appeal 2017-000371
Application 14/534,540
Technology Center 2800
Before MARKNAGUMO, JAMES C. HOUSEL, and
BRIAN D. RANGE, Administrative Patent Judges.
HOUSEL, Administrative Patent Judge.
DECISION ON APPEAL1
Pursuant to 35 U.S.C. § 134(a), Appellant2 appeals from the
Examiner’s decision rejecting claims 1-3, 8-10, 12-14, 16, 21, 22, 26, and
1 Our Decision refers to the Specification (Spec.) filed November 6, 2014,
the Examiner’s Final Office Action (Final Act.) dated July 28, 2015,
Appellants’ Appeal Brief (Appeal Br.) filed January 18, 2016, the
Examiner’s Answer (Ans.) dated July 28, 2016, and Appellants’ Reply Brief
(Reply Br.) filed September 28, 2016.
2 The Appeal Brief identifies Applicant, Maxim Integrated Products, Inc.
(“Appellant”), as the real party in interest. Appeal Br. 3.
Appeal 2017-000371
Application 14/534,540
28 as unpatentable under 35 U.S.C. § 103(a) over Hodel3 in in view of
Zuniga.4 We have jurisdiction over the appeal under 35 U.S.C. § 6(b).
We REVERSE, but enter a new ground of rejection pursuant to our
authority under 37 C.F.R. § 41.50(b).
STATEMENT OF THE CASE
The invention relates to a laterally configured, split gate power
MOSFET5 having a stepped gate oxide layer on a surface of a doped silicon
substrate and a split polysilicon gate layer (i.e., cut into two electrically
isolated gates) over the stepped gate oxide layer forming a first switching
gate and a second static gate. Spec. 6:2^4 and 6-9. The Inventors disclose
that the stepped gate oxide layer includes a first portion underneath the first
switching gate and a second portion underneath the second static gate,
wherein the first portion has a thickness less than the second portion. Id. at
6:4-6. According to the Inventors, this thickness variation ensures that
“[t]he rated gate-to-source voltage of the polysilicon switching gate is lower
than the rated gate-to[-]source voltage of the polysilicon static gate.” Id. at
6:15-17. In addition, the Inventors disclose that a portion of the static gate
extends over a drift region of the substrate, where the drift region is under a
field oxide filled trench formed in the substrate. Id. at 18:30-31. The
extended portion of the static gate, according to the Inventors, functions as a
field gate to establish a high breakdown voltage. Id. at 18:31-19:1.
3 Hodel et al., US 2009/0140372 Al, published June 4, 2009 (“Hodel”).
4 Zuniga et al., US 7,405,443 Bl, issued July 29, 2008 (“Zuniga”).
5 Metal-Oxide-Semiconductor Field-Effect Transistor.
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Appeal 2017-000371
Application 14/534,540
Appellant’s Figure 8, shown below, depicts laterally configured, split
gate power MOSFET 5006 in accordance with the claimed invention.
Appellant’s Figure 8 showing a laterally configured, split gate power
MOSFET
Claim 1, reproduced below from the Claims Appendix to the Appeal
Brief, is illustrative of the subject matter on appeal. Reference numerals
from Appellant’s Figure 8 above have been added to the corresponding
recited structure in the claim. In addition, the limitation at issue has been
italicized.
1. A power transistor [500] comprising:
a doped substrate [510] comprising a source [516], a first
channel region, a bridge [536], a second channel region, a drain
[518], and a trench [526] disposed between the drain and the
bridge, the trench defined within the doped substrate, wherein
6 Throughout this Decision, for clarity, we present labels to elements in
figures in bold font, regardless of their presentation in the original document.
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Application 14/534,540
the first channel region is positioned between the source and the
bridge, and the second channel region is positioned between the
bridge and the drain;
a first gate oxide layer [529] positioned on the substrate
over at least the first channel region;
a second gate oxide layer [528] positioned on the
substrate over at least the second channel region, wherein a
thickness of the first gate oxide layer is less than a thickness of
the second gate oxide layer;
a first gate [530] positioned on the first gate oxide layer
and over the first channel region; and
a second gate [532] positioned on the second gate oxide
layer and over the second channel region, wherein the first gate
is separated from the second gate such that at least a portion of
the bridge is uncovered by both the first gate and the second
gate, the second gate extending beyond the second gate oxide
layer.
Independent claim 14 similarly recites a split gate power transistor
having a second gate extending beyond the second gate oxide layer.
ANALYSIS
The Examiner has the initial burden of establishing a prima facie case
of obviousness based on an inherent or explicit disclosure of the claimed
subject matter under 35 U.S.C. § 103. In re Oetiker, 977 F.2d 1443, 1445
(Fed. Cir. 1992) (“[T]he examiner bears the initial burden, on review of the
prior art or on any other ground, of presenting a prima facie case of
unpatentability”). To establish a prima facie case of obviousness, the
Examiner must show that each and every limitation of the claim is described
or suggested by the prior art or would have been obvious based on the
knowledge of those of ordinary skill in the art. In re Fine, 837 F.2d 1071,
1074 (Fed. Cir. 1988).
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Application 14/534,540
There is no dispute that Hodel discloses a laterally configured, split
gate MOSFET substantially as recited in claims 1 and 14, except for the
recited difference in thickness in the first and second gate oxide layers and
for the limitation that the second gate extends beyond the second gate oxide
layer. Compare Final Act. 2-6 with Appeal Br. 12-13 and 15-16. There is
also no dispute that Zuniga discloses a split gate power transistor having first
and second gate oxide layers under first and second gates, respectively,
wherein the thickness of the first gate oxide layer is less than that of the
second gate oxide layer. Compare Final Act. 4-6 with Appeal Br. 12-13
and 15-16. Appellant does not challenge the Examiner’s conclusion that it
would have been obvious to have modified Hodel such that the first and
second gate oxide layers have different thicknesses in accordance with the
teaching of Zuniga. See Appeal Br. and Reply Br., generally.
Instead, Appellant contests the Examiner’s finding that Hodel
discloses or suggests that the second gate extends beyond the second gate
oxide layer, or that such feature was well known in the art. Appeal Br. 12-
13 and 15-16; Reply Br. 3-10. For the reasons explained in detail below,
we conclude the preponderance of the evidence supports Appellant’s
arguments on this point.
The Examiner sets forth three bases in support of the obviousness
over Hodel: 1) that Hodel’s second gate G2 is positioned over the second
gate oxide and extends over field oxide filled trench 126 as shown in
annotated Figure 2 (Ans. 3); 2) that it is well known in the art that “gate
oxide” is an oxide layer vertically separating a gate electrode and a portion
of substrate forming a channel region {id. at 4); and 3) that Appellant’s
written description teaches that the static gate is positioned over the second
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Application 14/534,540
gate oxide layer and extends over the field oxide filled trench, but does not
explicitly teach that the second gate oxide layer under the static gate is
removed or that the second gate extends beyond the second gate oxide layer
{id.).
With regard to the first basis listed above, as Appellant contends,
Hodel teaches that the gate oxide is present “over the workpiece 112, over
the wells 120 and 118, and the isolation region 126.” Hodel ^ 39. Thus,
Hodel explicitly teaches that the gate oxide extends over the isolation region.
The Examiner’s annotation to Hodel’s Figure 2 is erroneous because it fails
to reflect Hodel’s teaching that the gate oxide extends over isolation region
126.
Further, to the extent that the Examiner’s second basis purports to
defmitionally limit the gate oxide to only that portion of the gate oxide layer
that is actually underneath the gate AND over the channel region, such a
construction is contrary to HodeFs teaching that the gate oxide extends over
isolation region 126. Hodel ^ 39 (“A gate oxide (not shown) is formed over
. . . the isolation region 126.”) In addition, we note that although the
Examiner attempts to limit the meaning of “gate oxide,” the claims here
recite “gate oxide layer” which includes not only that portion of the oxide
layer under the gate, but also any other portion of the oxide layer. For
example, first gate oxide layer 529 in Appellant’s Figure 8 is not only
underneath switching gate 530, but also extends over N+ region 522 to
contact 524.
As to the Examiner’s third basis for finding Hodel teaches or suggests
the second gate extends beyond the second gate oxide layer, we note that the
Examiner has not questioned Appellant’s written descriptive support for the
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Application 14/534,540
limitation at issue. Indeed, the Examiner fails to address the disclosure of
Appellant’s drawings which clearly depict the gate oxide layer ending at the
trench and the static gate extending beyond the gate oxide layer over the
trench. See Figs. 2, 5, 6, and 8. MPEP § 2163(II)(A)(3)(a), Tj 3 (“An
applicant may show possession of an invention by disclosure of drawings or
structural chemical formulas that are sufficiently detailed to show that
applicant was in possession of the claimed invention as a whole.”) See, e.g.,
Vas-Cath Inc. v. Mahurkar, 935 F.2d 1555, 1563, 1565 (Fed. Cir. 1991)
(“drawings alone may provide a ‘written description’ of an invention as
required by § 112”); In re Wolfensperger, 302 F.2d 950 (CCPA 1962) (the
drawings of applicant’s specification provided sufficient written descriptive
support for the claim limitation at issue); Autogiro Co. of Am. v. United
States, 384 F.2d 391, 398 (Ct. Cl. 1967) (“In those instances where a visual
representation can flesh out words, drawings may be used in the same
manner and with the same limitations as the specification.”)”.)
In addition, the Examiner interprets Specification, page 27, lines 6-8,
to mean that “any portion of the polysilicon is removed, the oxide under the
polysilicon is removed with it. Or any part of the polysilicon is not
removed, the oxide under it would remain.” Ans. 4. Appellant contends that
the Specification disclosure to which the Examiner refers is directed to the
creation of gap 534 to form split gates and the bridge region, and is not
directed to the limitation at issue. Reply Br. 7. Appellant’s contention is
supported by the quoted disclosure from the Specification which makes clear
that a slice of the polysilicon layer and a portion underneath this slice are
removed. This disclosure clearly pertains to the formation of gap 534 and
not to the portion of the polysilicon layer overlying the transition region
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Application 14/534,540
between the second channel region and trench 526 nor to the portion of the
polysilicon layer overlying the trench.
Thus, the Examiner has not carried the burden of establishing, by a
preponderance of the evidence, the factual basis for the conclusion that the
claimed invention would have been obvious.
New Ground of Rejection under 37 C.F.R. § 41.50(b)
Notwithstanding our decision above regarding the Examiner’s
obviousness rejection of the claims over Hodel and Zuniga, we enter the
following new ground of rejection in accordance with our authority under
37 C.F.R. §41.50(b).
Claims 1-3, 8-10, 12-14, 16, 21, 22, 26, and 28 are unpatentable
under 35 U.S.C. § 103(a) over Hodel in view of AAPA7 and Zuniga. As
indicated above, there is no dispute that Hodel teaches a laterally configured,
split gate power transistor as recited in the claims, except for the recited
difference in thickness in the first and second gate oxide layers and for the
limitation that the second gate extends beyond the second gate oxide layer.
There is also no dispute, as indicated above, that Zuniga discloses a split
gate power transistor having first and second gate oxide layers under first
and second gates, respectively, wherein the thickness of the first gate oxide
layer is less than that of the second gate oxide layer. Likewise as indicated
above, Appellant does not challenge the Examiner’s conclusion that it would
have been obvious to have modified Hodel such that the first and second
7 Appellant’s Admitted Prior Art, Figure 2 and Spec. 4-5 (“AAPA”).
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Appeal 2017-000371
Application 14/534,540
gate oxide layers have different thicknesses in accordance with the teaching
of Zuniga.
The only limitation in dispute is the recitation in claims 1 and 14 that
the second gate extends beyond the second gate oxide layer. Appellant
discloses, as admitted prior art, that it was known to provide a gate
extending beyond the gate oxide layer over the shallow trench. Specifically,
Figure 2 shows that polysilicon gate layer 30 extends beyond gate oxide
layer 28 over shallow trench 26. Appellants disclose that the reason for
polysilicon gate layer 30 extending over the shallow trench is “to support
high drain-to-gate voltage.” Spec. 5:6-7. In addition, Appellants disclose
that
[i]f the polysilicon gate 30 were to instead terminate over the
thin gate oxide, this would result in too high a voltage across
the gate oxide and the power transistor would not function. As
such, the STI region [(trench 26)] and the polysilicon gate
extension over the STI region are necessary to drop the high
gate-to-drain voltage.
Id. at 5:14-18. These prior art admissions suggest that Hodel’s power
transistor would benefit from stopping the gate oxide layer at the trench such
that static gate G2 extends over the trench without the underlying gate oxide
layer in order to drop the high gate-to-drain voltage. It would, therefore,
have been obvious for one of ordinary skill in the art to have removed
Hodel’s gate oxide layer under static gate G2 over trench 126 in order to
drop the high gate-to-drain voltage as taught by AAPA.
DECISION
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Application 14/534,540
Upon consideration of the record, and for the reasons given above and
in the Appeal and Reply Briefs, the decision of the Examiner rejecting
claims 1-3, 8-10, 12-14, 16, 21, 22, 26, and 28 as unpatentable under
35 U.S.C. § 103(a) over Hodel in view of Zuniga is reversed.
However, a new ground of rejection of claims 1-3, 8-10, 12-14, 16,
21, 22, 26, and 28 as unpatentable under 35 U.S.C. § 103(a) over Hodel in
view of AAPA and Zuniga is entered.
This decision contains a new ground of rejection pursuant to
37 C.F.R. § 41.50(b) (effective September 13, 2004, 69 Fed. Reg. 49960
(August 12, 2004), 1286 Off. Gaz. Pat. Office 21 (September 7, 2004)).
37 C.F.R. § 41.50(b) provides “[a] new ground of rejection pursuant to this
paragraph shall not be considered final for judicial review.”
37 C.F.R. § 41.50(b) also provides that the appellant, WITHIN TWO
MONTHS FROM THE DATE OF THE DECISION, must exercise one of
the following two options with respect to the new ground of rejection to
avoid termination of the appeal as to the rejected claims:
(1) Reopen prosecution. Submit an appropriate amendment of the
claims so rejected or new evidence relating to the claims so rejected, or both,
and have the matter reconsidered by the examiner, in which event the
proceeding will be remanded to the examiner. . . .
(2) Request rehearing. Request that the proceeding be reheard under
§ 41.52 by the Board upon the same record. . . .
REVERSED
NEW GROUND OF REJECTION. 37 C.F.R, § 41,501b)
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