11178552 (B.P.A.I. Jul. 20, 2012)

Ex Parte Marks et al

Board of Patent Appeals and InterferencesJul 20, 2012

11178552 (B.P.A.I. Jul. 20, 2012)

UNITED STATES PATENT AND TRADEMARKOFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 11/178,552 07/11/2005 Kevin T. Marks 016295.1839 9298 7590 07/20/2012 Roger Fulghum Baker Botts L.L.P. One Shell Plaza 910 Louisiana Street Houston, TX 77002-4995 EXAMINER PATEL, NIMESH G ART UNIT PAPER NUMBER 2111 MAIL DATE DELIVERY MODE 07/20/2012 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE BOARD OF PATENT APPEALS AND INTERFERENCES ____________ Ex parte KEVIN T. MARKS and DON H. WALKER ____________ Appeal 2009-015247 Application 11/178,552 Technology Center 2100 ____________ Before KRISTEN L. DROESCH, DENISE M. POTHIER and ERIC B. CHEN, Administrative Patent Judges. DROESCH, Administrative Patent Judge. DECISION ON APPEAL Appeal 2009-015247 Application 11/178,552 2 STATEMENT OF THE CASE Appellants seek review under 35 U.S.C. § 134(a) of a second non- final rejection of claims 1, 2, 5-10, 13-17, 19 and 20.1 We have jurisdiction under 35 U.S.C. § 6(b). We REVERSE. BACKGROUND Appellants’ disclosed invention relates to a system and method for identifying inoperable connection points in a storage enclosure. Spec. 1, ll. 5-7. Claim 1 is illustrative and is reproduced below (disputed limitation in italics): 1. A method for identifying the operability of the connection points of a storage architecture, comprising: retrieving from a location in the storage architecture configuration data, wherein the configuration data identifies the configured connection points within the storage architecture, wherein the configuration data comprises a bit string, wherein the respective bits of the bit string correspond to individual connection points in the storage architecture, and wherein the respective bits of the bit string correspond to individual phys within a Serial Attached SCSI expander; performing a discovery process to attempt to discover the operability of each connection point within the storage architecture; comparing the successfully discovered and operable connection points to the configuration data to identify connection points that are configured as being connection points in the storage architecture but were not discovered as being operable as part of the discovery process; and performing at least one of reporting or repairing one or more of the connection points configured as being connection points in the storage architecture but were not discovered 1 Claims 3, 4, 11, 12 and 18 have been cancelled. Br. 2. Appeal 2009-015247 Application 11/178,552 3 as being operable as part of the discovery process. Rejections Claims 1, 2, 5-8, 16, 17, 19 and 20 stand rejected under 35 U.S.C. § 103(a), as unpatentable over Goodman (US 2006/0064542 A1), Johnson (US 2006/0230125 A1) and Sue (US 2006/0161714 A1). Claims 9, 10 and 13-15 stand rejected under 35 U.S.C. § 103(a), as unpatentable over Johnson and Sue. ISSUE Did the Examiner err in finding that the combination of Goodman, Johnson and Sue or the combination of Johnson and Sue fails to teach or suggest “the configuration data comprises a bit string, wherein the respective bits of the bit string correspond to individual connection points in the storage architecture,” as recited in claim 1 and similarly recited in independent claims 9 and 16? ANALYSIS We have reviewed the Examiner’s rejection in light of Appellants’ arguments in the Appeal Brief2 presented in response to the Non-Final Office Action (“NFOA”). We agree with Appellants’ conclusions and highlight and address specific findings and arguments for emphasis as follows. The Examiner finds that neither Goodman, nor Johnson teaches the disputed claim limitation. Ans. 4, 7. Instead, the Examiner relies on Sue for teaching a bit string or register to represent the link status of devices. NFOA 2 We refer to Appellants’ Amended Appeal Brief filed March 02, 2009. Appeal 2009-015247 Application 11/178,552 4 3, 6; Ans. 4, 7 (citing Sue ¶ 0028); see also Sue, Fig 4: Link Status Register 211a. We agree with Appellants’ argument that Sue does not teach or suggest that individual bits in the register correspond to individual connection points, or individual lanes. Br. 6. We further agree with Appellants that Sue only discloses that the number of lanes being used is kept in a Negotiation Link Width Register. Br. 6 (citing ¶ 0028); see also Sue, Fig. 4: Negotiation Link Width Register 211c; ¶¶ 0029, 0035, 0045-46; 0051-53. Moreover, the Examiner does not provide a sufficient factual basis to support the following additional findings presented in the Response to Appellants’ arguments: During operation, the status of the links (specifically the lanes (serial lines) are monitored since the number of lanes connected can decrease or changed (sic) (Paragraphs 12 and 44). Figure 1 shows that four lanes are used to connect the devices. One skilled in the art would recognize that a single bit holding logic one or logic zero is all that is required to represent connection status of a single lane in Sue’s device. Since there are four lanes, and any combination of lanes are connected, four bits would logically be needed to hold the status of the links, each bit representing a specific lane location (e.g., second lane of the four lanes) and status of that lane (connected or disconnected). Therefore, Sue does teach individual bits in the register correspond to individual connection points. Ans. 8. The Examiner does not direct us, and Sue is silent as to, the use of bits to represent a connection status of a lane or a lane location. Instead, Sue merely teaches that monitoring the connection status is based on a comparison of the number of serial lines (i.e., lanes) included in a set of a plurality of serial lines when an interrupt is received with the number of Appeal 2009-015247 Application 11/178,552 5 serial lines included in the set at initialization. Sue ¶ 0012; claim 8 (emphasis added). For all these reasons, we do not sustain the Examiner’s rejections of claims 1, 2, 5-8, 16, 17, 19 and 20 as obvious over Goodman, Johnson and Sue and claims 9, 10 and 13-15 as obvious over Johnson and Sue. DECISION We REVERSE the rejection of claims 1, 2, 5-10, 13-17, 19 and 20 under 35 U.S.C. § 103(a), as unpatentable over Goodman, Johnson and Sue. We REVERSE the rejection of claims 9, 10 and 13-15 under 35 U.S.C. § 103(a), as unpatentable over Johnson and Sue. REVERSED tj