Ex Parte MariggisDownload PDFBoard of Patent Appeals and InterferencesDec 18, 200910477221 (B.P.A.I. Dec. 18, 2009) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE ________________ BEFORE THE BOARD OF PATENT APPEALS AND INTERFERENCES ________________ Ex parte ATHANASE MARIGGIS ________________ Appeal 2009-001109 Application 10/477,221 Technology Center 2800 ________________ Decided: December 18, 2009 ________________ Before KENNETH W. HAIRSTON, JOHN A. JEFFERY, and THOMAS S. HAHN, Administrative Patent Judges. HAHN, Administrative Patent Judge. DECISION ON APPEAL Appellant invokes our review under 35 U.S.C. § 134 from the Examiner’s final rejection of claims 1-9. We have jurisdiction under 35 U.S.C. § 6(b). We affirm. Appeal 2009-001109 Application 10/477,221 2 STATEMENT OF THE CASE Appellant claims an electrical circuit and method for providing clock signals from first and second clock generators. Both clock generators have a first phase lock loop (PLL) and also a second PLL. The two first PLLs are each synchronized to a different reference clock source. The two second PLLs are connected to the first PLL for the first clock generator. If, however, there is no clock signal produced from the first PLL for the first clock generator, then the two second PLLs are connected to the other reference clock source provided from the first PLL for the second clock generator. The two second PLLs output clock signals.1 Claim 1 is illustrative: 1. A method for production of an internal clock in an electrical circuit having a first clock generator and a second clock generator, with the clock generators each having at least one connection for an external reference clock source and each having at least one first PLL and one second PLL, comprising: synchronizing the respective first PLLs of the clock generators to clock signals from respectively different reference clock sources, wherein the second PLL for the second clock generator and the second PLL for the first clock generator produce clock signals based on clock signals which are produced by the first PLL for the first clock generator, when the first PLL for the first clock generator produces clock signals, and the second PLL for the second clock generator and the second PLL for the first clock generator produce clock signals based on clock signals which are produced by the first PLL for the second clock generator as soon as the 1 See generally Figure 1; Spec. 5:24-36; 6:15-26; 10:33 – 12:8. Appeal 2009-001109 Application 10/477,221 3 second clock generator determines that no clock signals are being produced by the first PLL for the first clock generator. The Examiner relies on the following prior art references to show unpatentability: Leshem US 5,787,265 July 28, 1998 Imamura2 (“Tetsuya”)3 JP 07-297707 Oct. 11, 1995 The Examiner rejected claims 1-9 under 35 U.S.C. §103(a) as unpatentable over Leshem and Imamura. Rather than repeat the arguments of Appellant or of the Examiner, we refer to the Briefs and the Answer4 for their respective details. In this decision, we have considered only those arguments actually made by Appellant. Arguments that Appellant could have made but did not make have not been considered and are deemed to be waived. See 37 C.F.R. § 41.37(c)(1)(vii). Appellant’s Arguments Appellant collectively argues claims 1-9 by separately arguing for independent claim 1 (App. Br. 4-6). Accordingly, we select independent claim 1 as representative for the group. See 37 C.F.R. § 41.37(c)(1)(vii). 2 An English translation of this Japanese reference was entered in the record on Nov. 13, 2007, and it is that translation that is referred to and is cited for this decision as opposed to the prior entered machine language translation. 3 The Appellant and Examiner (Ans. 3) have referred to this Japanese reference as being Tetsuya. For consistency, we, in this opinion, also refer to the reference as Tetsuya. 4 We refer throughout this opinion to the Appeal Brief filed Mar. 21, 2007, the Answer mailed Nov. 9, 2007, and the Reply Brief filed Jan. 9, 2008. Appeal 2009-001109 Application 10/477,221 4 Appellant argues that the Examiner’s modification of Leshem’s input oscillators with Tetsuya’s PLL oscillator circuit fails to teach or suggest the appealed claim 1 limitations for both first and second clock generator circuits to receive different reference clock signals and produce clock signals from first PLLs (App. Br. 5). ISSUE Under § 103(a), has Appellant shown the Examiner erred by finding that Lesham and Tetsuya collectively teach or suggest PLL circuits being included in both first and second clock generator circuits that receive different reference clock signals and produce clock signals as recited in representative claim 1? FINDINGS OF FACT The record supports the following Findings of Fact (FF) by a preponderance of the evidence: 1. Leshem discloses a data storage system and implementing method, which includes a clock pulse generator 72 having two PLLs 102 and 103 that output a pair of clock pulses (CLCK “A” and CLCK “B”) from an input one of a pair of oscillators (80 and 82), such that when the initial input oscillator becomes defective the clock generator produces clock pulses from the other of the pair of oscillators (Leshem, col. 1, ll. 7-11; col. 6, ll. 18-27; col. 6, l. 57 – col. 7, l. 23; Fig. 4). 2. Tetsuya describes a phase-locked oscillation circuit, which is disclosed as having low phase noise, reduced power consumption, Appeal 2009-001109 Application 10/477,221 5 and as outputting an oscillation signal usable in various communications devices (Abstract, Tetsuya, ¶ [0001]). 3. The Tetsuya phase-locked oscillation circuit receives a reference oscillator 2 signal 20 that is input to a phase comparator 3 that outputs a comparison signal 30 to a temperature compensation loop circuit 4 for driving a voltage controlled oscillator 1 to output an oscillation signal 10 (Tetsuya, ¶¶ [0002], [0017]; Fig. 1). PRINCIPLES OF LAW An Examiner, in rejecting claims under 35 U.S.C. § 103, must establish a factual basis to support a legal conclusion of obviousness. See In re Fine, 837 F.2d 1071, 1073 (Fed. Cir. 1988). The Supreme Court has further explained that an obviousness rejection must be based on “‘some articulated reasoning with some rational underpinning to support the legal conclusion of obviousness’ . . . [H]owever, the analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim, for a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’l. Co. v. Teleflex, Inc., 550 U.S. 398, 418 (2007) (quoting In re Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006)). ANALYSIS Based on the record, we are not persuaded the Examiner erred in rejecting claims 1-9 under § 103. We agree with the Examiner’s findings and line of reasoning that Leshem teaches a method for producing clock signals from a first and a second clock generator, with each clock generator having an oscillator and a PLL (Ans. 3; FF 1). Leshem, though, is acknowledged by the Examiner as Appeal 2009-001109 Application 10/477,221 6 failing to teach that the first and second clock generator included oscillators have first PLL circuits as recited in representative claim 1 (Ans. 3). Turning to Tetsuya, the Examiner indicated that Tetsuya’s oscillator in Figure 1 has a PLL, and that this circuit would have been an obvious modification for the Leshem oscillator because “Tetsuya’s oscillator circuit has the advantage of small phase noise and small power consumption” (id.). Appellant contends as a distinction between claimed subject matter and the Examiner’s indicated modification of Leshem, that Leshem’s taught reference clocks are switched between clock generators, and “even if one were to place a PLL circuit inside Leshem’s Oscillators 80 and 82, the output would nonetheless still be a reference clock” (App. Br. 5). Further, Appellant asserts that “the term ‘clock signal’ is a well known term of art, and . . . a ‘reference signal’ is not a clock signal, as a clock signal drives a circuit and a reference signal does not” (App. Br. 6) (italics substituted for underlining emphasis). No factual evidence is submitted by Appellant to support this asserted difference in reference and clock signals, and, therefore, the assertion is an unsupported attorney argument and a conclusory statement that is deficient for rebutting a prima facie case of obviousness. In re Geisler, 116 F.3d 1465, 1470 (Fed. Cir. 1997). The Examiner addresses the Appellant’s assertion as to differences in Leshem’s and Tetsuya’s signals with an explanation that the rejection modification is to use Tetsuya’s phase-locked oscillation circuit as shown in Figure 1 for Leshem’s oscillators 80 and 82 (Ans. 6). Then the Examiner explains that the Tetsuya circuit to be substituted for Leshem’s oscillators 80 and 82 includes a phase lock loop (i.e., phase comparator 3, temperature compensation loop circuit 4 and voltage controlled oscillator 1) with an Appeal 2009-001109 Application 10/477,221 7 input reference oscillator 2 signal 20 (id.). Further, the Examiner indicates that Leshem teaches “that after the clock signal (output of 80 provided through switches 90 and 91) is generated [i.e., no longer is produced], the clock signal is switched (switches 90 and 91 select the output of oscillator 82)” (Ans. 7) (emphasis added). We concur with the Examiner’s findings that Leshem teaches that when the initial input oscillator (80 or 82) becomes defective, the clock generator 72 produces clock pulses (CLCK “A” and CLCK “B”) from the other of the pair of oscillators (82 or 80) (FF 1). Appellant responds with a new argument by asserting that Leshem teaches the use of a single clock reference (Reply Br. 2). As an initial matter, we find in contradiction to Appellant’s assertion that Leshem teaches two separate input oscillator signals (80 and 82) (FF 1) as opposed to a single clock reference. Additionally, whether Leshem teaches a single or two separate input oscillator signals is a matter raised for the first time on appeal in the Reply Brief, and, therefore, is deemed to be a waived argument. See Optivus Tech. Inc. v. Ion Beam Appl’ns S.A., 469 F.3d 978, 989 (Fed. Cir. 2006) (“[A]n issue not raised by an appellant in its opening brief . . . is waived.”) (citations and quotation marks omitted); see also Ex Parte Scholl, No. 2007-3653, slip op. at n.13 (BPAI Mar. 13, 2008) (informative), available at http://www.uspto.gov./web/offices/dcom/bpai/its/fd073653.pdf (same). Thus, we are not persuaded by Appellant’s distinction between reference and clock signal argument (App. Br. 5, 6). We agree with the Examiner that Leshem teaches that one of two separate oscillator signals 80 or 82 is input to PLLs 102 and 103 (Ans. 7; FF 1). Moreover, when the input oscillator signal becomes defective, another oscillator signal is input to Appeal 2009-001109 Application 10/477,221 8 PLLs 102 and 103 (id.). Consequently, we find that the Examiner’s relied- on evidence and reasoning, when considered as a whole, supports the prima facie obviousness rejection by teaching the claimed method of (1) synchronizing first PLLs for two clock generators with different reference clock sources; (2) producing clock signals from second PLLs for the two clock generators based on clock signals produced by the first PLL for the first clock generator; and (3) when no clock signals are produced by the first PLL for the first clock generator producing clock signals from second PLLs for the two clock generators based on clock signals produced by the first PLL for the first clock generator (Ans. 3, 4; FF 1-3). For the foregoing reasons, Appellant has not persuaded us of error in the Examiner’s rejection. Therefore, we will sustain the rejection of representative claim 1, and also claims 2-9 that fall with claim 1. CONCLUSION OF LAW Based on the findings of facts and analysis above, we conclude that the Appellant has not shown that the Examiner erred in rejecting claim 1-9 under § 103. ORDER The Examiner’s decision rejecting claims 1-9 is affirmed. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). AFFIRMED Appeal 2009-001109 Application 10/477,221 9 gvw K&L GATES LLP P.O. BOX 1135 CHICAGO, IL 60690 Copy with citationCopy as parenthetical citation