Ex Parte Marella et al

Patent Trial and Appeal Board

Jan 11, 2016

11939983 (P.T.A.B. Jan. 11, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
111939,983
61507 7590
Entropy Matters LLC
P.O. Box 2250
11/14/2007
01/12/2016
NEW YORK, NY 10021
FIRST NAMED INVENTOR
Paul Frank Marella
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
5222-05708/Pl 129/1 C 6952
EXAMINER
KIM,SUC
ART UNIT PAPER NUMBER
2899
MAILDATE DELIVERY MODE
01112/2016 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte PAUL FRANK MARELLA,
SHARON MCCAULEY, ELLIS CHANG, WILLIAM VOLK,
JAMES WILEY, STERLING WATSON,
SAGAR A. KEKARE, and CARL HESS
Appeal2014-000040
Application 11/939,983
Technology Center 2800
Before ADRIENE LEPIANE HANLON, CATHERINE Q. TIMM, and
JAMES C. HOUSEL, Administrative Patent Judges.
TIMM, Administrative Patent Judge.
DECISION ON APPEAL 1
STATEMENT OF CASE
Appellants2 appeal the Examiner's decision to reject claims 86-96
under 35 U.S.C. § 112 i-f 1 as lacking written descriptive support, claims 86,
90, and 93 under 35 U.S.C. § 112 i-f 2 as indefinite, and claims 86-96 under
1 In our opinion below, we refer to the Specification filed November 14,
2007 (Spec.), Final Office Action filed April 12, 2012 (Final), the Appeal
Brief filed January 30, 2013 (Br.), and the Examiner's Answer filed June 19,
2013 (Ans.).
2 Appellants identify the real party of interest as KLA-Tencor Technologies
Corporation. Br. 2.
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Application 11/939,983
35 U.S.C. § 102(b) as anticipated byNehmadi. 3'4 We have jurisdiction
under 35 U.S.C. §§ 6(b) and 134(a).
We AFFIRM.
The claims are directed to a method for monitoring fabrication of an
integrated circuit (IC) on a semiconductor wafer. Claim 86 is illustrative:
86. A method for monitoring fabrication of an
integrated circuit (IC) on a semiconductor wafer, comprising:
generating a product design profile (PDP) using an
electronic design automation (EDA) tool, the PDP comprising
an indication of a site in at least one layer of the IC that is more
susceptible to a process fault than other sites in the at least one
layer;
fabricating the at least one layer of the IC on the wafer;
and
applying a process monitoring tool to perform a
measurement at the site in the at least one layer responsively to
the PDP.
Claims Appendix at Br. 39.
OPINION
Written Descriptive Support
The Examiner rejects claim 86-96 under 35 U.S.C. § 112 i-f 1 as
lacking written descriptive support. Of particular concern to the Examiner is
language in the generating step of each of the independent claims.
3 Nehmadi et al., US 2005/0010890 Al published Jan. 13, 2005 (hereinafter
"N ehmadi").
4 The Examiner also objects to the drawings and the Specification. In so far
as these objections are related to the § 112 i-f 1 rejection, they stand or fall
with that rejection. Otherwise, the objections involve petitionable matters
outside our jurisdiction to review.
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Application 11/939,983
Specifically, the Examiner finds no support for the PDP comprising "an
indication of a site in at least one layer of the IC that is more susceptible to a
process fault than other sites in the at least one layer" as recited in claim 86,
the PDP comprising "an identification of a region in at least one layer of the
IC that is characterized by a periodic pattern" as recited in claim 90, and the
PDP comprising "an identification of a plurality of regions in at least one
layer of the IC and a respective criticality parameter for each of the regions
indicative of a maximum tolerable defect size in each of the regions" as
recited in claim 93. Final 10-11.
For the reasons we discuss below, we determine that Appellants have
not identified a reversible error in the Examiner's finding of lack of written
descriptive support.
Claim 86
Appellants contend that the generating step of claim 86 finds support
in the Specification on, for example, page 16, line 29 to page 17, line 3, page
24, line 8 to page 25, line 21, and page 32, lines 14--25. Br. 5-6.
Page 16, line 29 to page 17, line 3 of Appellants' Specification reads:
The IC design may be developed using any method or system
known in the art such as electronic design automation (EDA),
computer aided design (CAD), and other IC design software.
Such methods and systems may be used to generate the circuit
pattern database from the IC design.
Spec. 16:29-17:3. This portion of the Specification discloses using IC
design software such as electronic design automation in the process of
creating the IC design and for generating the IC circuit pattern database
reflecting that design.
The Specification at page 24, line 8 to page 25, line 21 describes an
example of "how individual layer data for an IC can be manipulated to
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Application 11/939,983
identify DCA [Do Not Care Areas] on a wafer." Spec. 24:8-9. Do Not Care
Areas (DCA) are areas of the wafer, such as dummy pads and other areas
that do not form an electrical element of a semiconductor device. Spec.
23: 17-21. Because these areas do not form an electrical element of the
device, it may not matter if they contain a defect and thus defects in the
DCA may be ignored if the defects do not affect electronic circuit elements
in other layers. Id. The Specification describes identifying the DCA areas
and creating DCAl data for the layer, and further filtering out any DCA that
may contain defects potentially contributing to defects in the electronic
circuits of a layer above or below it to obtain the actual DCA data (DCA2).
Spec. 24: 19-22. This DCA data, possibly along with designer intent data or
information about the criticality of different areas of the wafer, may be sent
to inspection systems such as the reticle inspection system or the wafer
inspection system. Spec. 25: 13-21. The inspection system uses the DCA
to limit inspection to non-DCA, i.e., the areas that matter or matter the most,
or to filter out nuisance defects within the DCA. Id.
The page 32, line 14--25 portion of the Specification discloses an
embodiment using information about a reticle or designer intent data and the
fault-tolerance of the design to identify defects that may be discarded or
classified as nuisance defects. Spec. 32:14--16. Although not entirely clear,
it appears that the information used to identify nuisance defects relates to the
relative dimensions of the design features and the redundancy of the circuit
elements. Spec. 32: 16-25.
The test for compliance with the written description requirement is
"whether the disclosure of the application relied upon reasonably conveys to
those skilled in the art that the inventor had possession of the claimed
subject matter as of the filing date." Ariad Pharmaceuticals, Inc. v. Eli Lilly
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Application 11/939,983
& Co., 598 F.3d 1336, 1351 (Fed. Cir. 2010) (en bane). The question is not
whether the claims use the same words as the Specification, but whether the
concept of the claim limitation is in the Specification. See In re Anderson,
471F.2d1237, 1244 (CCPA 1973) ("The question, as we view it, is not
whether 'carrying' was a word used in the specification as filed but whether
there is support in the specification for employment of the term in a claim; is
the concept of carrying present in the original disclosure?").
After reviewing the entirety of the Specification as originally filed,
particularly considering the portions cited by Appellants in light of their
arguments, we agree with the Examiner that the concept of generating a
product design profile (PDP) using an electronic design automation (EDA)
tool, the PDA comprising an indication of a site in at least one layer of the
IC that is more susceptible to a process fault than other sites in the at least
one layer is not supported by the written description of Appellants'
Specification. Ans. 3.
The Specification discloses using an electronic design automation tool
to develop the integrated circuit (IC) design and to generate a circuit pattern
database, but there is no indication that the resulting IC design is the product
design profile (PDP) of the claim because the IC design and circuit pattern
database generated by the electronic design automation tool is not disclosed
in the Specification as "comprising an indication of a site in at least one
layer of the IC that is more susceptible to a process fault than other sites in
the at least one layer."
The Specification discloses identifying Do Not Care Areas (DCA),
but these areas are merely areas containing dummy pads and other elements
that are not part of the electrical circuits of the semiconductor device on the
wafer; they are not "an indication of a site in at least one layer of the IC that
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Application 11/939,983
is more susceptible to a process fault than other sites in the at least one
layer." First, the meaning of process fault in the context of the claim is
unclear. The Specification does not refer to process faults. Appellants
equate a process fault with "defects that may adversely affect a layer above
or below the layer," but provide no evidence that the ordinary artisan would
so define "process fault." Br. 6.
Even if we were to equate the IC design with the product design
profile (PDP), the DCA and non-DCA with the sites, and the process faults
with the defects above and below the layer as argued by Appellants, the
Specification would fail to disclose incorporating the DCA data into the IC
design generated by the EDA. Nor can we say that the written description
conveys that the PDP includes an indication that the DCA in at least one
layer of the IC is more susceptible to defects than other sites (DCA) in the at
least one layer in a way that the ordinary artisan would be able to discern
from the written description.
The Specification further discloses using designer intent data and the
fault-tolerance of the design to determine which defects may be discarded or
classified as nuisance defects, but there is no disclosure of generating a
product design profile (PDP) with data indicating which sites are more
susceptible to process faults. Again, the Specification fails to ascribe any
meaning to "process fault" and the meaning of the phrase is unclear.
Even assuming the defects in the layers above and below the layer
with the DCAI data are "process faults" and the IC design is the PDP, the
Specification fails to reasonably convey possession of the concept of
including within the IC design generated by the EDA the indication of
susceptibility.
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Because the Specification does not use the terms product design
profile (PDP) and process fault, it is not clear that these terms refer to the IC
design and defects above and below the layer, respectively, disclosed in the
Specification.
Appellants have not convinced us of a reversible error in the
Examiner's rejection of claim 86 as lacking written descriptive support.
Claim 90
Claim 90 reads:
90. A method for monitoring fabrication of an integrated
circuit (IC) on a semiconductor wafer, comprising:
generating a product design profile (PDP) using an
electronic design automation (EDA) tool, the PDP comprising
an identification of a region in at least one layer of the IC that
is characterized by a periodic pattern;
fabricating the at least one layer of the IC on the wafer;
and
applying a process monitoring tool to perform a
measurement in the region on the at least one layer responsively
to the periodic pattern.
Claims Appendix at Br. 39-40 (emphasis added).
Appellants again point to the Specification at page 16, line 29 to page
17, line 3 and page 24, line 8 to page 25, line 21 for support. Appellants
further point to page 29, lines 18-28.
Appellants reproduce Page 29, lines 18-28 of the Specification with
emphasis as follows:
Fig. 4 is a flow chart illustrating a computer-implemented
method that includes detecting defects on a wafer by analyzing
data generated by inspection of the wafer in combination with
data representative of a reticle. The method includes obtaining
data representative of the reticle, as shown in step 44. The data
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Application 11/939,983
representative of the reticle may include macro level
information (like the SRAM). The macro level information
may include repeating small figures (like cells) amassed into
intermediate level figures (like memory pages), which can be
brought up together to the macro level. The data representative
of the reticle may also be discrete micro features in the logic.
Such data may be described in MEBES files, GDSII files or
other standard file descriptions of the reticle. The files may
include designer intent data as described above such as
designations that distinguish between different types of portions
of the reticle, features, or portions of features on the reticle.
Br. 12.
Appellants contend that this portion of the Specification is equivalent
to the portion of claim 90 we emphasized above. Id.
Again, the Specification does not use the words product design profile
(PDP) much less define what is included in such a profile. The Specification
describes generating an IC design and an IC design circuit pattern database
using electronic design automation (EDA), and also describes generating
data by inspecting the \x;afer in combination \x1ith data representative of the
reticle. The Specification does not disclose a product design profile that is
both generated by EDA and includes "an identification of a region in at least
one layer of the IC that is characterized by a periodic pattern."
The disclosure on page 29 does not reasonably convey possession of
the concept of including in the PDP "an identification of a region in at least
one layer of the IC that is characterized by a periodic pattern." The
Specification merely discloses organizing data into small figures (like cells)
amassed into intermediate level figures (like memory pages), which can be
brought up together to the macro level. That the data is divided into small
figures or cells says little about the periodicity of the data within the cells or
in the circuit pattern laid down using the data.
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Application 11/939,983
Appellants have not convinced us of a reversible error in the
Examiner's rejection of claim 90.
Claim 93
Claim 93 reads:
93. A method for monitoring fabrication of an integrated
circuit (IC) on a semiconductor wafer, comprising:
generating a product design profile (PDP) using an
electronic design automation (EDA) tool, the PDP comprising
an identification of a plurality of regions in at least one layer of
the IC and a respective criticality parameter for each of the
regions, indicative of a maximum tolerable defect size in each
of the regions;
fabricating at least one layer of the IC on the wafer; and
applying a process monitoring tool to perform a
measurement in one or more of the regions in at least one layer
responsively to the respective criticality parameter.
Claims Appendix at Br. 40-41.
Appellants rely upon the same portion of the Specification they relied
upon in disputing the Examiner's rejection of claim 86. Br. 19--21.
Appellants contend that the disclosure on page 32, lines 14--23 is equivalent
to the claim limitation emphasized above. Br. 20. That portion of the
Specification reads:
According to another embodiment, information about a
reticle or designer intent data and the fault-tolerance of the
design may be used to determine which defects may be
discarded or classified as nuisance defects. For example,
detecting defects may include discarding defects or events in
one portion of the wafer that have a lateral dimension smaller
than the predetermined threshold associated with this portion of
the wafer if other features in this portion of the wafer have a
lateral dimension greater than the predetermined threshold.
Such defects may be discarded since such defects may not be
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Application 11/939,983
"killer defects." In a different example, defects in one portion
of the wafer may be discarded if an element of a circuit in this
portion of the wafer or in a section of the design has a
predetermined amount of redundancy and if the defects in this
portion of the wafer do not exceed a predetermined density
threshold.
Spec. 32:14--23.
We agree with the Examiner that Appellants' Specification fails to
reasonably convey possession of the required product design profile (PDP).
Ans. 9--10. Although the Specification describes using designer intent data
and the fault tolerance of the design to determine which defects may be
discarded or classified as nuisance defects, where the data is located is not
disclosed. A product design profile is not described. Nor is determining
which defects are not "killer defects" based on differences in lateral
dimension within a region necessarily include identification of a respective
criticality parameter for each of the plurality of layer regions, indicative of a
maximum tolerable defect size in each of the regions. The Specification
does not convey the concept of the claim.
Appellants have not convinced us of a reversible error in the
Examiner's rejection of claim 93 as lacking written descriptive support.
Dependent Claims
Appellants argue that each of the limitations of the dependent claims
is supported by the Specification. Br. 8-26. For the reasons cited by the
Examiner, we determine that a preponderance of the evidence supports the
Examiner's rejection of the dependent claims. Ans. 3-11.
Indefiniteness
The Examiner rejects claims 86, 90, and 93 under 35 U.S.C. § 112 i-f 2
as indefinite. The Examiner determines that "process fault" as used in claim
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Application 11/939,983
86, "characterized by a periodic pattern" in claim 90, and "indicative of a
maximum tolerable defect size" in claim 93 are indefinite. 5 Final 4--5.
Claim 86
Appellants contend that "process fault" is a term commonly used and
understood by one of ordinary skill in the art, and is equivalent to the term
"defect" as used in the Specification. Br. 26-27. But in arguing against the
written description rejection, Appellants equate "process fault" with "defects
that may adversely affect a layer above or below the layer." Br. 6. It is not
clear that a process fault is generically the same as a defect, limited to
defects above and below a layer in which DCA have been identified, only
defects arising due to processing, a fault in the process itself, or something
else. The Specification does not use the words "process fault" much less
provide any guidance on the meaning of the phrase. Nor do Appellants
provide any convincing evidence that the term has an ordinary and
customary meaning in the art. We agree with the Examiner that the phrase
as used in Appellants' claim is indefinite. Ans. 11-12.
Appellants have not convinced us of a reversible error in the
Examiner's rejection of claim 86 as indefinite.
Claim 90
Claim 90 recites "a region in at least one layer of the IC that is
characterized by a periodic pattern."
Appellants contend that "characterized by a periodic pattern" is a term
commonly used and understood by one of ordinary skill in the art, and that it
5 It is not clear why the Examiner confined the rejection to the independent
claims. The dependent claims do not appear to remedy the indefiniteness
issues raised by the Examiner. In the event of further prosecution, the
Examiner should consider extending the rejection to all the claims.
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Application 11/939,983
is clear in light of the disclosure of the Specification. Br. 27. Appellants
point to a disclosure in the Specification stating that:
Determining parameters for defect detection may be based on
the types of the portions of the wafer. The parameters that may
be varied may include, for example, a threshold value, a type of
algorithm, and/or an inspection method (i.e., array or random).
Spec. 31 :27-29 (emphasis Appellants'). According to Appellants, it would
be clear to the ordinary artisan that array and random areas on a wafer are
characterized by different periodic patterns. Id.
It is not clear how doing an inspection method randomly or in an array
clarifies the meaning of "characterized by a periodic pattern" as that phrase
is used in claim 90. In claim 90, it is a region in at least one layer of the IC
that is characterized by a periodic pattern. It is simply not clear what the
phrase means when referring to a single region of a layer of an integrated
circuit (IC). Nor is it clear what has the periodic pattern, a feature within the
circuitry or some other aspect of the region.
The Examiner questions whether the "periodic pattern" refers to the
circuit layout pattern or the occurrence of the defects pattern. Ans. 12. That
question has not been addressed by Appellants. No reply brief was filed.
Appellants have not convinced us that the Examiner reversibly erred
in rejecting claim 90 as indefinite.
Claim 93
The phrase of claim 93 containing the language the Examiner
determines to be indefinite reads "the PDP comprising an identification of a
plurality of regions in at least one layer of the IC and a respective criticality
parameter for each of the regions, indicative of a maximum tolerable defect
size in each of the regions." Claim 93 (emphasis added).
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Application 11/939,983
Appellants contend that "indicative of a maximum tolerable defect
size" as used in claim 93 would be clear to one of ordinary skill in the art,
particularly in light of the disclosure in the Specification at page 32, lines
14--25. Br. 28-29. Appellants do not provide any further explanation. Id.
The problem here is that, as pointed out by the Examiner, there is no
supporting disclosure that clearly describes a process or step for performing
an identification of a plurality of regions in at least one layer of the IC and a
respective criticality parameter for each of the regions that is "indicative of a
maximum tolerable defect size." Final 5. The only portion of the page 32
disclosure relating to defect size relates to a lateral dimension smaller than a
predetermined threshold, but neither the smaller lateral dimension or the
threshold is clearly indicative of a maximum tolerable defect size as the
defect is discarded if other features in the same portion of the wafer have a
lateral dimension greater than the predetermined threshold. It is not clear
what parameter is "indicative of a maximum tolerable defect size," and thus
1t 1s unclear what the phrase means in the context of the claim and disclosure
as a whole. In a vacuum, the phrase may appear to be clear, but when one
attempts to understand the phrase in light of the Specification, the phrase
becomes unclear.
Appellants have not convinced us the Examiner reversibly erred in
rejecting claim 93 as indefinite.
Anticipation
The Examiner rejects claims 86-96 as anticipated by Nehmadi.
Appellants do not dispute that Nehmadi anticipates the subject matter of the
claims. Instead, Appellants contend that Nehmadi is not available as prior
art. Br. 30-38. But because Appellants' claims lack written descriptive
support, the claims are not entitled to a filing date pre-dating N ehmadi' s
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effective filing date. Thus, Appellants have not convinced us of a reversible
error in the Examiner's rejection of claims 86-96 as anticipated by
Nehmadi.
CONCLUSION
We sustain the Examiner's rejections.
DECISION
The Examiner's decision is affirmed.
TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l ).
AFFIRMED
bar
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