Ex Parte Mar

Board of Patent Appeals and Interferences

Jun 24, 2010

09943062 (B.P.A.I. Jun. 24, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
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Ex parte MONTE MAR
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Appeal 2009-004958
Application 09/943,062
Technology Center 2800
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Decided: June 24, 2010
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Before ROBERT E. NAPPI, CARL W. WHITEHEAD JR., and
BRADLEY W. BAUMEISTER, Administrative Patent Judges.

NAPPI, Administrative Patent Judge.

DECISION ON APPEAL
Appeal 2009-004958
Application 09/943,062

This is a decision on appeal under 35 U.S.C. § 134(a) of the rejection
of claims 1 through 3, 5, 7 through 9, 11, 12, 14, 15, 17 through 22, and 24.
We reverse.

INVENTION
The invention is directed toward a power management circuit for an
analog circuit such as an operational amplifier. See page 6 of Appellant’s
Specification. Claim 1 is reproduced below:1
1. A programmable analog circuit block having
programmable power management comprising:
an operational amplifier circuit for driving a load;
a plurality of paired current sources located within said
operational amplifier circuit, wherein a first current source in
each pair is coupled in a first parallel configuration to a first
node that is coupled to transistors receiving input voltages to
said operational amplifier circuit, and a second current source in
each pair is coupled in a second parallel configuration to an
output of said operational amplifier circuit, wherein a ratio of
the amount of current between said current sources of each pair
of current sources is proportionally equal;
a bias supply signal for generating a given bias voltage;
and
a plurality of configuration bits for selectively applying
said given bias voltage to an associated pair of current sources
in order to modulate the performance of said operational
amplifier circuit.

1 Because claim 1 is directed towards an apparatus (see 35 U.S.C. § 101
(setting forth the statutory classes eligible for patent protection)), we
provisionally interpret the claim term “bias supply signal” as intended to
read “bias supply signal line.” Likewise, we provisionally interpret the
claim term “a plurality of configuration bits,” which refers to data per se, as
intended to read “two inputs capable of providing a plurality of
configuration bits.”
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Appeal 2009-004958
Application 09/943,062

REFERENCES
The Examiner’s Answer cites the following prior art references:
Kitsukawa US 4,999,519 Mar. 12, 1991
Nishimaki JP 404095408A Mar. 27, 1992
Kondo JP 405055842A Mar. 5, 1993
Tadao JP 406021732A Jan. 28, 1994
REJECTION AT ISSUE
The Examiner has rejected claims 1 through 3, 5, 7 through 9, 11, 12,
14, 15, 17 through 22, and 24 under 35 U.S.C. § 103(a) as being
unpatentable over Tadao, Nishimaki, Kondo, and Kitsukawa. Answer 3-7.

ISSUE
Did the Examiner err in finding that that the combination of the
references teaches configuration bits for selectively applying the given bias
voltage to an associated pair of current sources as recited in the independent
claims?

FINDINGS OF FACT
1) Tadao teaches an operational amplifier circuit in which at least two
values can be selected for the bias current of the current source. Para
0007 of translation.
2) The bias voltage for current source, item 105, is shown in all the
Figures as 104. The two values of bias voltage are switched in time
division and alternate between –Vb1 and –Vb2 to adjust the current
flow through the current source. See, Paras 0008, 0017, 0018, 0019,
and Figures 1, 3(a), 3(b) and 4 of the Tadao translation.
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Appeal 2009-004958
Application 09/943,062

ANALYSIS
Appellant’s arguments have persuaded us that the Examiner erred in
rejecting claims 1 through 3, 5, 7 through 9, 11, 12, 14, 15, 17 through 22,
and 24. Independent claim 1 recites “a plurality of paired current sources”
and “a plurality of configuration bits for selectively applying said given bias
voltage to an associated pair of current sources.” Independent claim 11
includes a similar limitation. Independent claim 17 recites “sending a bias
voltage signal, in response to said first group of configuration bits, to a
selected group of paired current sources from a plurality of paired current
sources.” Thus, each of the independent claims recites that there are a
plurality of paired current sources and that a bias voltage is selectively
applied to a pair of current sources.
Appellant argues that Tadao teaches applying a plurality of bias levels
to both current sources in a time division manner. Reply Brief 5. Appellant
argues that “[s]electively applying a plurality of bias voltages to a single
current source is not equivalent to selectively applying a bias voltage to a
plurality of current sources.” Further, Appellant asserts that Nishimaki and
Kondo each teach selectively adding or removing one or more current
sources but does not teach selectively applying a bias voltage. Reply Brief 5
and 6. We concur with Appellant.
The Examiner finds that Tadao teaches a circuit with analog variable
current sources and a bias circuit for the transistors, and that Tadao does not
teach a plurality of paired current sources or “a plurality of configuration
bits, each bit for selectively cutting in and selectively removing the first and
second current source in associated [sic] in order to modulate the
performance of the operational amplifier circuit..” Answer 4. The
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Appeal 2009-004958
Application 09/943,062

Examiner relies upon Nishimaki and Kondo to teach variable current sources
where bits are used to selectively cut in and selectively remove one or more
current sources. Answer 4. These findings by the Examiner do not address
the claim limitations, as the claims do not refer to cutting in or removing a
current source but rather to selectively applying a bias voltage. While
Appellant’s Specification teaches applying a bias voltage may have the
effect of cutting in or removing a current source, the Examiner has not
shown that the Nishimaki or Kondo cut in or remove the current source by
selectively applying a bias voltage as claimed. Further, while Tadao teaches
controlling the current source by adjusting the bias voltage (FF 1 and 2),
Tadao similarly does not teach that cutting in or removing a current source
by selectively applying the bias voltage. Accordingly, we conclude that the
Examiner has not demonstrated that the combination of the references teach
configuration bits for selectively applying a given bias voltage to an
associated pair of current sources as recited in the independent claims 1, 11
and 17. Accordingly we will not sustain the Examiner’s rejection of claims
1 through 3, 5, 7 through 9, 11, 12, 14, 15, 17 through 22, and 24.

ORDER
The decision of the Examiner to reject claims 1 through 3, 5, 7
through 9, 11, 12, 14, 15, 17 through 22, and 24 is reversed.

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Appeal 2009-004958
Application 09/943,062

REVERSED

ELD

CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT
SAN JOSE, CA 95134-1709
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