Ex Parte Manning

Patent Trial and Appeal Board

Jun 25, 2015

11495499 (P.T.A.B. Jun. 25, 2015)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/495,499 07/28/2006 H. Montgomery Manning 02-1164.02/FLE
(MICS:0125
4490
7590 06/26/2015
Michael G. Fletcher
FLETCHER YODER
P.O. Box 692289
Houston, TX 77269-2289
EXAMINER
SMITH, BRADLEY
ART UNIT PAPER NUMBER
2817
MAIL DATE DELIVERY MODE
06/26/2015 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
_________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
__________

Ex parte H. MONTGOMERY MANNING
__________

Appeal 2013-002541
Application 11/495,4991
Technology Center 2800
___________

Before ADRIENE LEPIANE HANLON, CATHERINE Q. TIMM, and
JAMES C. HOUSEL, Administrative Patent Judges.

HANLON, Administrative Patent Judge.

DECISION ON APPEAL

A. STATEMENT OF THE CASE
The Appellant filed an appeal under 35 U.S.C. § 134 from a final rejection
of claims 1‒4 and 6‒15.2 We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM and enter a new ground of rejection under 37 C.F.R.
§ 41.50(b).
The claimed subject matter is directed to a method for fabricating a device,
such as a memory device. Spec. 1, ll. 11‒12.

1 According to the Appellant, the real party in interest is Micron Technology, Inc.
Appeal Brief dated July 2, 2012 (“App. Br.”), at 2.
2 Claims 16, 17, and 19‒21 are also pending and have been allowed by the
Examiner.
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Application 11/495,499

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Independent claims 1 and 9 are reproduced below from the Claims Appendix
of the Appeal Brief. The limitations at issue are italicized.
1. A method for fabricating a device, the method comprising:
depositing a dielectric etch stop layer directly on a plurality of
wordlines disposed in an array portion of a substrate and a plurality of
gates disposed in a peripheral portion of the substrate;
removing the dielectric etch stop layer from the peripheral
portion of the substrate;
removing only a portion of the dielectric etch stop layer from
the array portion of the substrate;
depositing a dielectric layer over each of the dielectric etch stop
layer, the array portion and the peripheral portion; and
removing a plurality of portions of the dielectric layer from
each of the dielectric etch stop layer, the array portion and the
peripheral portion to at least partially expose a conductive element
associated with at least one of the plurality of wordlines.
App. Br. 15 (emphasis added).
9. A method for fabricating a device with a dielectric etch stop
layer, the method comprising:
forming a first plurality of structures in an array portion of a
substrate and a second plurality of structures in a peripheral portion of
the substrate, wherein the second plurality of structures comprises
gates;
depositing a dielectric etch stop layer directly on the first
plurality of structures and the second plurality of structures;
removing the dielectric etch stop layer from the second plurality
of structures;
etching a pattern into the dielectric etch stop layer to expose at
least one of the first plurality of structures;
depositing a dielectric layer over the first plurality of structures
in the array portion of the substrate and the second plurality of
structures in the peripheral portion of the substrate; and
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removing a portion of the dielectric layer over the first plurality
of structures with an etchant to expose at least one of the first plurality
of structures and removing a portion of the dielectric layer over the
second plurality of structures with the etchant to expose a conductive
element of at least one of the second plurality of structures, wherein
the etchant is more selective to the dielectric layer than the dielectric
etch stop layer.
Id. at 16 (emphasis added).
The claims on appeal stand rejected as follows:
(1) claims 1, 2, 6, 8, 9, 12, and 14 under 35 U.S.C. § 102(b) as anticipated
by Ahn;3
(2) claims 3 and 10 under 35 U.S.C. § 103(a) as unpatentable over Ahn in
view of Himeno;4
(3) claims 4, 7, 11, and 15 under 35 U.S.C. § 103(a) as unpatentable over
Ahn in view of Huang;5 and
(4) claim 13 under 35 U.S.C. § 103(a) as unpatentable over Ahn in view
of Lee.6
Claims 1‒4 and 6‒15 also stand rejected on the ground of nonstatutory
obviousness-type double patenting as being unpatentable over claims 1‒13 and 15
of US 7,659,211. Final Office Action dated January 26, 2012, at 2. The Appellant
does not contest the rejection. See App. Br. 5 (indicating that the obviousness-type
double rejection “is not the subject of this appeal”). Therefore, the Examiner’s
decision to reject claims 1‒4 and 6‒15 on the ground of obviousness-type double
patenting is summarily affirmed.

3 US 5,874,330, issued February 23, 1999.
4 US 2001/0028080 A1, published October 11, 2001.
5 US 6,184,076 B1, issued February 6, 2001.
6 US 6,326,270 B1, issued December 4, 2001.
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Application 11/495,499

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The remaining rejections are sustained for reasons set forth in the
Examiner’s Answer dated October 10, 2012 (“Ans.”). We add the following for
emphasis.
B. DISCUSSION
1. Rejection under 35 U.S.C. § 102(b)
The Examiner finds Ahn discloses a method for fabricating a semiconductor
device comprising, inter alia, the steps of depositing dielectric layer 26 and
removing a plurality of portions of dielectric layer 26 to at least partially expose
conductive element 22. Ans. 2; see also Ahn Figs. 2d‒2g. The Examiner’s
annotated Ahn Figure 2d, reproduced below, is illustrative. Ans. 10.

Annotated Ahn Fig. 2d is a sectional view showing a step for
fabricating a semiconductor device in accordance
with Ahn’s disclosed invention.7

7 The left hand portion of the device depicted in Ahn Fig. 2d is the peripheral
region (II) and the right hand portion of the device is the cell or array region (I) of
substrate 21. Ahn, col. 3, ll. 27‒31.
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The Appellant does not direct us to any error in the Examiner’s finding that
Ahn removes a plurality of portions of dielectric layer 26 to expose conductive
element 22. See App. Br. 8 (indicating that removal of dielectric layer 26 “occur[s]
in stages”). However, the Appellant argues that Ahn completely removes layer 26
contrary to the language of claims 1 and 9. See id. at 5 (arguing that “the
independent claims require exposing a conductive element while removing some,
but not all, of a dielectric layer”). For this reason, the Appellant argues that Ahn
does not anticipate the claims on appeal. Id. at 11.
To support their argument, the Appellant directs our attention to the
following language in claim 1: “‘removing the dielectric etch stop layer’”8 and
“‘removing a plurality of portions of the dielectric layer.’” App. Br. 7 (citing
claim 1). Likewise, the Appellant directs our attention to the following language in
claim 9: “‘removing the dielectric etch stop layer’” and “‘removing a portion of
the dielectric layer.’” Id. (citing claim 9). The Appellant argues:
These claim terms are different and, as such, cannot be interpreted to
have the same meaning. Since “removing the dielectric etch stop
layer” clearly refers to the complete removal of the dielectric etch stop
layer, “removing a portion of the dielectric layer” cannot mean the
complete removal of the dielectric layer.
In other words, to interpret “removing a plurality of portions of
the dielectric layer” or “removing a portion of the dielectric layer” to
mean the complete removal of the dielectric layer would be contrary
to the plain meaning of the claims.
Id.
The Appellant’s argument is not persuasive of reversible error. The
Examiner correctly points out that “the features upon which applicant relies (i.e.,

8 There is no dispute on this record that Ahn describes depositing and removing a
dielectric etch stop layer according to the method recited in the Appellant’s claims
1 and 9.
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not removing the entirety of the dielectric layer) are not recited in the rejected
claim(s).” Ans. 8.
According to the method disclosed in Ahn, a portion of dielectric layer 26 is
removed over both the array portion (I) and the peripheral portion (II) of the
substrate. See Ahn Fig. 2e; Ahn, col. 3, ll. 55‒59. Subsequently, the remaining
portion of dielectric layer 26 is removed over the array portion (I) of the substrate
to expose conductive element 22.9 See Ahn Fig. 2g. Thus, Ahn describes
removing a plurality of portions of dielectric layer 26 to expose conductive
element 22 as recited in claim 1 and removing a portion of dielectric layer 26 in the
array portion (I) of the substrate to expose at least one structure (i.e., conductive
element 22) as recited in claim 9. See Ans. 9‒10.
We recognize that removal of the portion(s) of dielectric layer 26 to expose
conductive element 22 results in a complete removal of the dielectric layer in the
array portion (I) of Ahn’s substrate. Nonetheless, contrary to the Appellant’s
arguments, claims 1 and 9 merely recite that the conductive element is exposed by
removing a portion or a plurality of portions of the dielectric layer. Claims 1 and 9
do not require “not completely removing a dielectric layer” as argued by the
Appellant. Reply Br. 7.10
For the reasons set forth above and reasons provided in the Examiner’s
Answer, the § 102(b) rejection of claims 1 and 9 is sustained. The Appellant does
not present arguments in support of the separate patentability of the remaining
claims on appeal. See App. Br. 12‒13. Therefore, the § 102(b) rejection of claims

9 As shown in Ahn Figure 2g, a portion of dielectric layer 26 (i.e., 26a) remains
over the peripheral portion (II) of the substrate.
10 Reply Brief dated December 10, 2012.
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2, 6, 8, 12, and 14 and the § 103(a) rejections of claims 3, 4, 7, 10, 11, 13, and 15
are sustained.
2. New ground of rejection
Claims 1‒4 and 6‒8 are rejected under 35 U.S.C. § 112, second paragraph,
as being indefinite.
Claim 1 recites “removing a plurality of portions of the dielectric layer from
each of the dielectric etch stop layer, the array portion and the peripheral portion to
at least partially expose a conductive element associated with at least one of the
plurality of wordlines.” App. Br. 15 (emphasis added). According to claim 1,
wordlines are disposed in an array portion of the substrate and gates are disposed
in a peripheral portion of the substrate. Id.; see also id. at 3 (identifying the
wordlines as “e.g., 310‒316” in Fig. 15). Thus, it is unclear on this record how
removing a plurality of portions of the dielectric layer from the peripheral portion
would expose a conductive element associated with at least one of the plurality of
wordlines.
Furthermore, a plurality of portions of the dielectric layer are removed from
the dielectric etch stop layer in the array portion, not “from each of the dielectric
etch stop layer[] [and] the array portion” as recited in claim 1, to “at least partially
expose a conductive element associated with at least one of the plurality of
wordlines.” App. Br. 15 (emphasis added). Thus, claim 1 does not accurately
define the Appellant’s invention.
C. DECISION
The decision of the Examiner is affirmed.
Claims 1‒4 and 6‒8 also stand rejected under 35 U.S.C. § 112, second
paragraph. This is a new ground of rejection under 37 C.F.R. § 41.50(b) which
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provides that “[a] new ground of rejection . . . shall not be considered final for
judicial review.”
37 C.F.R. § 41.50(b) also provides that the Appellant, WITHIN TWO
MONTHS FROM THE DATE OF THE DECISION, must exercise one of the
following two options with respect to the new grounds of rejection to avoid
termination of the appeal as to the rejected claims:
(1) Reopen prosecution. Submit an appropriate amendment of
the claims so rejected or new evidence relating to the claims so
rejected, or both, and have the matter reconsidered by the examiner, in
which event the proceeding will be remanded to the examiner. . . .

(2) Request rehearing. Request that the proceeding be reheard under
§ 41.52 by the Board upon the same record. . . .
No time period for taking any subsequent action in connection with this
appeal may be extended under 37 C.F.R. § 1.136(a)(1).
AFFIRMED; 37 C.F.R. § 41.50(b)
bar