Ex Parte Madeira et alDownload PDFPatent Trial and Appeal BoardDec 29, 201613338111 (P.T.A.B. Dec. 29, 2016) Copy Citation United States Patent and Trademark Office UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O.Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 13/338,111 12/27/2011 Paul Madeira 09-OT-141US02 (5200029) 5018 30424 7590 01/03/2017 ADOMPt - ST f fir sit filed TTS/Asia^ EXAMINER 255 S. Orange Avenue, Suite 1401 Orlando, EL 32801 COLE, BRANDON S ART UNIT PAPER NUMBER 2842 NOTIFICATION DATE DELIVERY MODE 01/03/2017 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): creganoa@addmg.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte PAUL MADEIRA and JOHN HOGEBOOM1 Appeal 2014-004723 Application 13/338,111 Technology Center 2800 Before CHUNG K. PAK, CATHERINE Q. TIMM, and GEORGE C. BEST, Administrative Patent Judges. PAK, Administrative Patent Judge. DECISION ON APPEAL This is a decision on an appeal under 35 U.S.C. § 134(a) from the Examiner’s decision2 finally rejecting claims 1-21, which are all of the claims pending in the above identified application. We have jurisdiction under 35 U.S.C. § 6(b). We AFFIRM. 1 The real party in interest is said to be STMicroelectronics (Canada) Inc. Appeal Brief filed September 19, 2013 (“App. Br.”) at 1. 2 Final Action entered April 22, 2013 (“Final Act.”) at 2-12 and the Examiner’s Answer entered December 31, 2013 (“Ans.”) at 3-13. Appeal 2014-004723 Application 13/338,111 STATEMENT OF THE CASE The subject matter on appeal is directed to “clock circuits, and more particularly clock circuits] used with Serializer/Deserializer (SerDes) circuits.” Spec. 12. Figure 2, which illustrates such clock circuits, is reproduced below: m \ LOW LOOP BANDWIDTH 125 MHz REFERSMCE• CLOCK PHASE- FREQUENCY COMPARATOR 1 S CLOCKING EXAMPLE r255 m sis GHz \ LG VCO MARY LOCAL VCOS 232 125MHJ | FEEDBACKS CLOCK | MODEST POWER DOF, TO RESONANT TANK ’-204 FEEDBACK DIVIDER --- (E.G.+5Q) SINGLE PHASE CLOCK DISTRIBUTION CHAIN S-20S >■[> >-t>.l~>- V 210 Fig. 2 Figure 2 is a schematic diagram of a clock circuit Figure 2 shows that “clocking circuit 200 according to an embodiment of the invention includes a 125 MHz reference clock, a phase-frequency comparator 202, a feedback divider 204 (e.g. +50) and a central 6.25 GHz LC VCO 206 [(first VCO (Voltage-Controlled Oscillator) 206)] in a loop configuration.” Spec. 121. “A single phase clock distribution chain 210 is coupled to the junction between [first] VCO 206 and divider 204” and is also coupled to second VCO (Voltage- Controlled Oscillator) 212 that “provides a plurality of phased output clock signals 208.” Id. 2 Appeal 2014-004723 Application 13/338,111 Details of the appealed subject matter are recited in illustrative claims 1,11, and 21,3 which are reproduced below from the Claims Appendix of the Appeal Brief (with disputed limitations in italicized form): I. A clock circuit comprising: a comparator for receiving a reference clock signal; a first Voltage-Controlled Oscillator (VCO) coupled to the comparator; a feedback divider coupled between the first VCO and the comparator; a clock distribution chain coupled to the feedback divider and the first VCO; and a second VCO coupled to the clock distribution chain for providing an output clock signal, wherein the comparator, the first VCO, and the feedback divider form a feedback loop, and wherein the clock distribution chain and the second VCO are outside of the feedback loop. II. A clock circuit comprising: a comparator for receiving a reference clock signal; a first Voltage-Controlled Oscillator (VCO) coupled to the comparator, wherein the first VCO is a first type of VCO circuit; a feedback divider coupled between the first VCO and the comparator; a clock distribution chain coupled to the feedback divider and the first VCO; and a second VCO coupled to the clock distribution chain for providing an output clock signal, wherein the second VCO is a second type of VCO circuit, wherein the comparator, the first VCO, and the feedback divider form a feedback loop, and wherein the clock distribution chain and the second VCO are outside of the feedback loop. 3 Appellants argue common limitations in independent claims 1,11, and 21 and do not separately argue dependent claims 2-10 and 12-20. App. Br. 4-5. Therefore, for purposes of this appeal, we limit our discussion to claim 1. 37 C.F.R. § 41.37(c)(l)(iv) (2012). 3 Appeal 2014-004723 Application 13/338,111 21. A method of providing a plurality of phased clock signals comprising: within a feedback loop: comparing a reference clock signal to a feedback signal; transferring a result of the comparison to a first Voltage- Controlled Oscillator (VCO); dividing an output signal provided by the first VCO to generate the feedback signal; and outside of the feedback loop: providing the output signal to a plurality of second VCOs to generate the plurality of phased clock signals, wherein the first VCO and second VCO are different types of VCO circuits. App. Br. 7-9, Claims Appendix. The Examiner maintains the following grounds of rejection:4 1. Claims 1-3, 7, 9, 11-13, 17, 19, and 21 under 35 U.S.C. §102(b) as anticipated by the disclosure of Saint-Laurent (US 2006/0006918 A1 published Jan. 12, 2006); 2. Claims 4, 6, 8, 14, 16, and 18 under 35 U.S.C. § 103(a) as unpatentable over the disclosure of Saint-Laurent; 3. Claims 5 and 15 under 35 U.S.C. § 103(a) as unpatentable over the combined disclosures of Saint-Laurent and Droege et al. (“Droege”) (US 2008/0002801 Al published Jan. 3, 2008); and 4. Claims 10 and 20 under 35 U.S.C. §103(a) as unpatentable over the combined disclosures of Saint-Laurent and Deng et al. (“Deng”) (US 2009/0140817 Al published Jun. 4, 2009). final Act. 2-12 and Ans. 3-13. Appellants seek review of these grounds of rejection. App. Br. 3. 4 The Examiner has withdrawn the rejection of claim 7 under 35 U.S.C. §112, second paragraph, set forth in the final Action. Ans. 10. 4 Appeal 2014-004723 Application 13/338,111 DISCUSSION Upon consideration of the evidence on this appeal record in light of the respective positions advanced by the Examiner and Appellants, we find no harmful error in the Examiner’s rejections of claims 1-3, 7, 9, 11-13, 17, 19, and 21 under 35 U.S.C. § 102(b) and claims 4-6, 8, 10, 14-16, 18, and 20 under 35 U.S.C. § 103(a). Accordingly, we sustain the Examiner’s §§ 102(b) and 103(a) rejections of the above claims for the reasons set forth in the Final Action and the Answer. We add the following primarily for emphasis and completeness. To prevail in an appeal to this Board, Appellants must adequately explain or identify reversible error in the Examiner’s §§ 102(b) and 103(a) rejections. See 37 C.F.R. § 41.37(c)(l)(iv) (2012); see also In re Jung, 637 F.3d 1356, 1365-66 (Fed. Cir. 2011) (explaining that even if the examiner had failed to make a prima facie case, the Board would not have erred in framing the issue as one of reversible error because it has long been the Board’s practice to require an appellant to identify the alleged error in the examiner’s rejections). Here, there is no dispute that Saint-Laurent shows a clock circuit comprising phase-frequency detector 420 corresponding to the recited comparator for receiving a reference clock signal, first voltage-controlled oscillator 450, feedback divider 460 coupled between first voltage-controlled oscillator 450 and phase- frequency detector 420 (comparator), high frequency global clock distribution network 110 (corresponding to the recited clock distribution chain) coupled to first voltage-controlled oscillator 450 and feedback divider 460, and second voltage- controlled oscillator 450 located in PLL 210 coupled to high frequency global clock network 110 (the recited clock distribution chain) for providing an output clock. Compare Ans. 3-7, with App. Br. 4-5; see also Saint-Laurent Figs. 3 and 4 5 Appeal 2014-004723 Application 13/338,111 and 43 (“FIG. 4 illustrates a circuit schematic of an example phase-lock loop (PLL)... [which] may serve as a master PLL 120 [in FIG. 3] arranged to receive an incoming clock (i.e., system clock signal) and generate an output clock (i.e., global clock signal)...[and] may also serve as an individual slave PLL 210A-210C [in FIG. 3] arranged to receive an incoming clock (i.e., global clock signal) and generate an output clock”) and 44 (“FIG. 4 may comprise.. .a feedback circuit which includes a phase-frequency detector 420, a charge pump 430, a loop filter 440, a voltage-controlled oscillator 450, and a second divider 460 for providing local feedback to the phase-frequency detector 420 within the PLL (120/210)...”) Nor is there any dispute that “Saint-Laurent teaches in paragraph [0030] that PLL 120 is a master PLL that receives a SYSTEM CLOCK and PLLs 210A-210C are slave PLLs that receive a clock [signal] from the clock distribution chain 110. Therefore, the first and second VCOs are different types.” Compare Ans. 6-7, with App. Br. 4-5. Appellants only contend that “the second VCO of Saint-Laurent is shown in FIG. 4 thereof to be part of the feedback loop, not outside of the feedback loop as claimed.” App. Br. 4 This contention is not well taken. As correctly found by the Examiner, Saint-Laurent teaches the comparator, the first VCO, and the feedback divider form a feedback loop as required by claims 1,11, and 21. See, e.g., Ans. 4 and Saint-Laurent || 43 and 44. Specifically, Saint-Laurent teaches using such feedback loop shown in Figure 4 as master PLL 120 of Figure 3. Saint-Laurent || 43 and 44 (“FIG. 4 illustrates a circuit schematic of an example phase-lock loop (PLL)... [which] may serve as a master PLL 120 [in FIG. 3].. .FIG. 4 may comprise.. .a feedback circuit which includes a phase- frequency detector 420 [corresponding to the recited comparator], a charge pump 430, a loop filter 440, a voltage-controlled oscillator 450 [corresponding to the 6 Appeal 2014-004723 Application 13/338,111 recited first VCO] and a second divider 460 [corresponding to the recited divider] for providing local feedback to the phase-frequency detector 420 [corresponding to the recited comparator] within the PLL [120]” of Figure 3.) The Examiner also correctly finds that high frequency global clock network 110 (the recited clock distribution chain) and VCO 450 of Figure 4 located in slave PLLs 210A-210C (corresponding to the recited second VCO of the second feedback loop) are outside of the first feedback loop comprising, inter alia, the comparator, the first VCO, and the feedback divider located within master PLL 120 of Figure 3 as required by claims 1,11, and 21. See, e.g., Ans. 4 and 143 (“FIG. 4 illustrates a circuit schematic of an example phase-lock loop (PLL)... [which] may also serve as an individual slave PLL 210A-210C [in FIG. 3]”). Accordingly, we find that Appellants do not identify harmful error in the Examiner’s rejections of claims 1-3, 7, 9, 11-13, 17, 19, and 21 under 35 U.S.C. § 102(b) and claims 4-6, 8, 10, 14-16, 18, and 20 under 35 U.S.C. § 103(a). ORDER In view of the foregoing, the decision of the Examiner to reject claims 1-21 is AFFIRMED. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv). AFFIRMED 7 Copy with citationCopy as parenthetical citation