Ex Parte MacInnis

Patent Trial and Appeal Board

Feb 20, 2014

10850911 (P.T.A.B. Feb. 20, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte ALEXANDER MACINNIS
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Appeal 2011-009964
Application 10/850,911
Technology Center 2400
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Before KALYAN K. DESHPANDE, MICHAEL R. ZECHER, and
PETER P. CHEN, Administrative Patent Judges.

DESHPANDE, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2011-009964
Application 10/850,911

2
STATEMENT OF CASE1
Appellant seeks review under 35 U.S.C. § 134(a) of a final rejection
of claims 1-17, the only claims pending in the application on appeal. We
have jurisdiction over the appeal pursuant to 35 U.S.C. § 6(b).
We REVERSE and ENTER A NEW GROUND OF REJECTION
PURSUANT TO 37 C.F.R. § 41.50(b).

Appellant invented a method and circuit for providing data to a video
decoder. Specification ¶¶ 0015-0016.
An understanding of the invention can be derived from a reading of
exemplary claim 1, which is reproduced below:
1. A method of providing data to a video decoder, said method
comprising:
comparing a target address to a plurality of memory
address ranges;
when the target address is within one of the plurality of
memory address ranges:
examining a particular one of a plurality of
indicators associated with the memory address range, the
particular one of the plurality of indicators associated
with the memory address and indicating whether a data
word at the target address is in a cache; and
providing a data word at a cache address
associated with the particular one of the plurality of
indicators to the video decoder; and
providing the data word at the target address from
another memory, when the target address is not within one of
the plurality of memory ranges or when the particular one of the

1 Our decision will make reference to Appellant’s Appeal Brief (“App. Br.,”
filed Aug. 16, 2010), Reply Brief (“Reply Br.,” filed May 25, 2011), the
Examiner’s Answer (“Ans.,” mailed Mar. 25, 2011), and Final Rejection
(“Final Rej.,” mailed Dec. 15, 2009).
Appeal 2011-009964
Application 10/850,911

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indicators indicates that the data word at the target address is
not in the cache.

REFERENCES
The Examiner relies on the following prior art:
Robb
Robertson
Huang
US 4,682,283
US 5,850,632
US 6,694,420 B2
July 21, 1987
Dec. 15, 1998
Feb. 17, 2004

REJECTIONS
Claims 1, 3, 4, 7, and 9-13 stand rejected under 35 U.S.C. § 102(e) as
being anticipated by Huang. Ans. 4-7.
Claims 2, 5, 6, 8, and 15-17 stand rejected under 35 U.S.C. § 103(a)
as being unpatentable over Huang and Robertson. Ans. 7-8.
Claim 14 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Huang and Robb. Ans. 8-9.

ISSUE
The issue of whether the Examiner erred in rejecting claims 1-17 as
being anticipated by, or unpatentable over, the cited prior art turns on
whether Huang describes the following claim limitations: (1) “comparing a
target address to a plurality of memory address ranges,” as recited in
independent claim 1, and similarly recited in independent claim 9; (2) an
“indicator[] associated with the memory address and indicating whether a
data word at the target address is in a cache,” as recited in independent claim
1; and (3) a “bit [that] indicates whether a data word in the cache . . . stores
data from the memory address,” as recited in independent claim 9.

Appeal 2011-009964
Application 10/850,911

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ANALYSIS
Claims 1, 3, 4, 7, and 9-13 rejected under 35
U.S.C. § 102(e) as being anticipated by Huang
Appellant first contends that Huang fails to describe comparing a
target address to a plurality of memory address ranges, as recited by
independent claims 1 and 9. App. Br. 7. Appellant specifically argues that,
while Huang may disclose comparing a target address with a single address
range, Huang fails to describe comparing a target address to a plurality of
memory address ranges. Id. We agree with Appellant.
Huang describes an address range checking circuit. Ans. 4 (citing
Huang col. 6, ll. 48-50). The address range checking circuit is “operable to
determine if a 32-bit address, A[31:0] is within the range of a sixteen (16)
entry stack beginning at the 32-bit base address, B[31:0].” Huang col. 6, ll.
48-50. Huang further describes six regions in memory in which an address
A may be situated with respect to the stack frame. Ans. 10 (citing Huang
col. 7, l. 64 – col. 8, l. 4; fig. 6). Although Huang illustrates a plurality of
memory regions or address ranges where a target address may be located,
Huang compares a target address to only a single memory range and does
not compare a target address to the plurality of memory address ranges.
We find, however, that comparing a target address to a plurality of
memory address ranges was known to a person with ordinary skill in the art,
as taught by both Robertson and Robb. Robertson discloses that “[e]ach
generated external address is compared to the address ranges of the memory
configuration cache entries.” Robertson, Abstract. Robb also illustrates that
comparing a target address to a plurality of ranges was old and well known.
In particular, Robb discloses an address range comparison system that
“compare[s] multiple ranges to determine the position of a selected address
Appeal 2011-009964
Application 10/850,911

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with respect to each of those multiple ranges.” Robb col. 8, ll. 16-18. It
would have been obvious to one of ordinary skill in the art at the time of the
invention to have modified Huang, which describes comparing a target
address to a single range, to include a feature that compares a target address
to multiple ranges, as disclosed by both Robertson and Robb. Such a
modification would have made the comparator of Huang more robust and
versatile. Robb col. 8, ll. 27-29. Accordingly, we conclude that a person
with ordinary skill in the art would have found it obvious to modify Huang
with Robb and the results of such a modification would still yield a location
of the target address and, therefore, such a result is nothing more than a
predictable result. See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 421
(2007).
Because this rationale has not been presented by the Examiner, we
designate this rejection as a new ground of rejection pursuant to 37 C.F.R.
§ 41.50(b). Accordingly, claims 1, 3, 4, 7, and 9-13 are rejected under 35
U.S.C. § 103(a) as unpatentable over: (1) Huang and Robertson; and (2)
Huang and Robb. Because Appellant presents additional arguments alleging
error in the Examiner’s rejection of claims 1, 3, 4, 7, and 9-13, we will
consider those now.
Appellant further contends that Huang fails to discloses “examining a
particular one of a plurality of indicators associated with the memory
address range, the particular one of the plurality of indicators associated with
the memory address and indicating whether a data word at the target address
is in a cache,” as recited by independent claim 1, and similarly recited by
independent claim 9. App. Br. 8-9. Appellant specifically argues that
Huang fails to disclose an indicator associated with the memory address and
Appeal 2011-009964
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indicating whether a data word at the target address is located in a cache.
App. Br. 9.
We disagree with Appellant. The broadest reasonable interpretation
of the aforementioned claim limitation requires the examination of an
indicator, where the indicator indicates whether a data word at the target
address is in a cache.
Huang describes an address range checking circuit that includes an
adder, two comparators, and a gate. Huang col. 6, ll. 44-47. The checking
circuit determines if an address is within a stack by utilizing both
comparators. Huang col. 6, ll. 47-67. Huang defines a stack as “a segment
of continuous memory with a base address and an index address that is used
to store temporary data used to execute a subroutine in a program.” Huang
col. 6, ll. 34-36. The second comparator compares the target address to the
base address and outputs the result. Huang col. 6, ll. 53-58. This output
result indicates whether the target address is within a memory range. Huang
col. 6, ll. 62-67. If the target address is within a cache, the first comparator
outputs the result and, subsequently, fetches the stored temporary data (i.e.,
data word) stored at the target address to execute a subroutine in a program.
Huang col. 5, ll. 62-63; col. 6, ll. 25-26. As such, the comparator, and the
results of the comparison, as described in Huang, is an indicator that
indicates whether a target address is within a memory range. Accordingly,
we are not persuaded by Appellant’s argument that Huang fails to describe
the examination of an indicator, where the indicator indicates whether a data
word at the target address is in a cache, as claimed.
Appellant contends that Huang fails to describe a bit that indicates
whether a data word is in a cache, as recited by independent claim 9. App.
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Br. 10. Independent claim 9 is distinguished from independent claim 1
because it requires that the indicator is a bit. We are not persuaded by this
argument. Huang describes that the results of the comparator indicates
whether a data word is in a cache. Huang specifically describes that there is
a comparison of bits (Huang col. 6, ll. 50-60) and, therefore, we agree with
the Examiner that Huang describes a bit that indicates whether a data word is
in a cache, as claimed.

Claims 2, 5, 6, 8, and 14-17 rejected under 35 U.S.C. § 103(a)
as being unpatentable over the cited prior art
Appellant does not provide any separate and distinct arguments in
support of claims 2, 5, 6, 8, and 14-17 and, therefore, we do not find error in
the Examiner’s rejection of these claims. However, we note that claims 2, 5,
6, 8, and 14-17 depend from independent claims 1 and 9, and claims 1 and 9
are now rejected under a new ground. Accordingly, we will denominate the
rejections of claims 2, 5, 6, 8, and 14-17 as new grounds. That is, claims 2,
5, 6, 8, and 15-17 are rejected under 35 U.S.C. § 103(a) as unpatentable over
Huang and Robertson, and claim 14 is rejected under 35 U.S.C. § 103(a) as
unpatentable over Huang and Robb based on the rationale discussed supra.

CONCLUSION
The Examiner erred in rejecting claims 1-17.
However, a new ground of rejection is entered under 37 C.F.R.
§ 41.50(b). We newly reject claims 1-17 under 35 U.S.C. § 103(a) as being
unpatentable over the cited prior art, as designated above.

Appeal 2011-009964
Application 10/850,911

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DECISION
To summarize, our decision is as follows:
 The Examiner’s rejection of claims 1-17 is reversed.
 A new ground of rejection is entered 37 C.F.R. § 41.50(b). We newly
reject claims 1-17 under 35 U.S.C. § 103(a) as being unpatentable
over the cited prior art, as designated above.

REVERSED
37 C.F.R. § 41.50(b)

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