Ex Parte Ma et al

Board of Patent Appeals and Interferences

Oct 26, 2010

10389368 (B.P.A.I. Oct. 26, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/389,368 03/14/2003 Haibing Ma X-1300 US 1351
24309 7590 10/27/2010
XILINX, INC
ATTN: LEGAL DEPARTMENT
2100 LOGIC DR
SAN JOSE, CA 95124
EXAMINER
PHAM, CHRYSTINE
ART UNIT PAPER NUMBER
2192
MAIL DATE DELIVERY MODE
10/27/2010 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________
BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________
Ex parte HAIBING MA, L. JAMES HWANG, JEFFREY D. STROOMER,
and ROGER B. MILNE
____________
Appeal 2009-004909
Application 10/389,3681
Technology Center 2100
____________

Before LANCE LEONARD BARRY, JEAN R. HOMERE,
and DEBRA K. STEPHENS, Administrative Patent Judges.

HOMERE, Administrative Patent Judge.

DECISION ON APPEAL2

1 Filed on March 14, 2003. The real party in interest is Xilinx, Inc. (App.
Br. 1.)
2 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, or for filing a request for rehearing,
as recited in 37 C.F.R. § 41.52, begins to run from the “MAIL DATE”
(paper delivery mode) or the “NOTIFICATION DATE” (electronic delivery
mode) shown on the PTOL-90A cover letter attached to this decision.
Appeal 2009-004909
Application 10/389,368

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I. STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) (2002) from the
Examiner’s final rejection of claims 14 and 16 through 27. (App. Br. 1.)
Claims 1 through 13, 15, and 28 have been cancelled. (Id.) We have
jurisdiction under 35 U.S.C. § 6(b) (2008).
We reverse.
Appellants’ Invention
Appellants invented a method for translating a software program from
a dynamically-typed language, such as Matlab or Perl, to a hardware
description language (“HDL”). (Spec. 1, para. [0001] & [0003].)
Illustrative Claim
Independent claim 14 further illustrates the invention as follows:
14. A method for translating a first program in a dynamically-typed
language to a second program in a hardware description language,
comprising:

generating a control flow graph of the first program, the graph
having nodes that represent blocks of code and edges that represent
control flow between the blocks of code;

generating a static single assignment (SSA) program from the
first program and the control flow graph, wherein assignments of Ф()
functions to respective renamed variables are inserted at blocks of
code that correspond to join points in the graph, and each Ф() function
is specified with input arguments corresponding to type-defining
occurrences of a variable that is visible at the join point;

wherein each input argument in at least one Ф() function
corresponds to a different data type assigned to the variable;

resolving type differences between arguments to the Ф()
functions;
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wherein resolving comprises for each variable having
assignments of different data types, defining a named variable to be of
a composite data type that is sufficient for storage of each of the
different data types;

inserting, for each Ф() function, assignment statements in the
blocks of code that correspond to nodes leading to the join points in
the graph, and removing each Ф() function from the SSA program,
each assignment statement being an assignment of a type-defining
occurrence of a variable, in the block of code that corresponds to the
node leading to a join point, to a renamed variable; and

translating the SSA program to the second program in the
hardware description language.

Prior Art Relied Upon
The Examiner relies on the following prior art as evidence of
unpatentability:
Banerjee 2004/0019883 A1 Jan. 29, 2004
(filed Jan. 26, 2001)

C. Scott Ananian, “Reconfigurable Cryptography—A Hardware
Compiler for Cryptographic Applications,” (May 1997) at
http://cscott.net//Projects/ele580a/writeup.pdf. (hereinafter “Ananian”).

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Rejections on Appeal3
The Examiner rejects claims 14, 16 through 20, 23 through 25, and 27
under 35 U.S.C. § 103(a) as being unpatentable over the combination of
Banerjee and Ananian.
Appellants’ Contentions
Appellants contend that Ananian’s disclosure of utilizing Ф()
functions for determining the registers required for implementing a loop
does not teach functions for resolution of different data types assigned to a
variable. (App. Br. 3-4.) Appellants also argue that Ananian’s disclosure of
converting to single static assignment (“SSA”) form and inserting a Ф()
function statement does not teach inserting further assignment statements
into the blocks of code in the SSA program based on the Ф() function, let
alone removing the Ф() function. (Id. at 4.) Further, Appellants allege that
Ananian fails to disclose a “type-defining occurrence,” as recited in
independent claim 14. (Id. at 4-5.) Moreover, Appellants contend that
Ananian’s disclosure of a SSA form in which every variable receives exactly
one assignment during its lifetime does not necessarily suggest “each input
argument in at least one Ф() function corresponds to a different data type
assigned to a variable,” as recited in independent claim 14. (Id. at 5.)
Additionally, Appellants argue that independent claim 14 requires
both inserting assignments to Ф() functions and inserting assignment
statements for each Ф() function. (Reply Br. 3.) Appellants also allege that

3 Appellants do not separately argue the Examiner’s rejection of dependent
claims 21, 22, and 26 under 35 U.S.C. § 103(a) as being unpatentable over
the combination of Banerjee, Ananian, and Bhansali. (App. Br. 3; see also
Fin. Rej. 13.) Consequently, we will treat dependent claims 21, 22, and 26
as standing or falling with independent claim 14. See 37 C.F.R § 41.37
(c)(1)(vii).
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figures 1 and 2 of Ananian do not depict any insertion of comparable
assignment statements. (App. Br. 4; Reply Br. 3-4.) Rather, Ananian
discloses renaming of variables, whereas the claimed invention is directed to
both generating the SSA form and inserting further assignment statements
into the blocks of code in the SSA program based on the Ф() function.
(App. Br. 4; Reply Br. 3-4.) Moreover, Appellants contend that the
Examiner’s conclusion that “assignment statements are inserted prior to the
inserting of Ф() functions” is incorrect because in order to insert assignment
statements for each Ф() function, the SSA program with the Ф() function
must already exist. (Reply Br. 3.) Finally, Appellants argue that there is
insufficient rationale for the proffered combination. (App. Br. 5; Reply Br.
6-7.)
Examiner’s Findings and Conclusions
The Examiner finds that since independent claim 14 previously inserts
Ф() functions at joint points in the graph, the assignment statements are
inserted prior to inserting the Ф() functions. (Ans. 8.) The Examiner also
finds that figure 2 of Ananian depicts generating a SSA program from a first
program. (Ans. 9.) Moreover, the Examiner finds that Ananian discloses
that the same variable (V) is assigned two times in two assignment
statements (i.e., V1 and V2). (Id.) The Examiner finds that when Ananian
discloses generating the SSA program from the first program, the variable
(V) is renamed and, therefore, amounts to an additional assignment of value-
defining occurrence of a variable. (Id.) Additionally, the Examiner finds
that the assignment of (V3) is an additionally assignment statement that is
based on a previous assignment. (Id. at 9-10.)
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Further, the Examiner finds that Banerjee’s disclosure of generating a
SSA program to represent or rename variables of type Real, which can take
on values of different types (i.e., integer or Real), teaches “a different data
type assigned to the variable,” as claimed. (Id. at 10-11.) Finally, the
Examiner finds that there is sufficient rationale for the proffered
combination. (Id. at 11-12.)

II. ISSUE
Have Appellants shown that the Examiner erred in concluding that the
combination of Banerjee and Ananian renders independent claim 14
unpatentable? In particular, the issue turns on whether:
(a) the proffered combination teaches “each Ф() function is
specified with input arguments corresponding to type-defining occurrences
of a variable that is visible at the join point,” as recited in independent claim
14;
(b) the proffered combination teaches “wherein each input
argument in at least one Ф() function corresponds to a different data type
assigned to the variable,” as recited in independent claim 14; and
(c) the proffered combination teaches “removing each Ф() function
from the SSA program,” as recited in independent claim 14.

III. FINDINGS OF FACT
The following Findings of Fact (“FF”) are shown by a preponderance
of the evidence.
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Ananian
1. Ananian discloses a compiler that creates hardware structures
for cryptographic algorithms. (2: Intro.) In particular, Ananian discloses
utilizing optimized quadruples to generate and compile behavioral VHDL
code to hardware. (6: SEC. 4.3.)
2. Ananian discloses that SSA form is an intermediate format that
allows optimizations to occur efficiently and easily. (4-5: SEC. 4.2.2.)
Ananian discloses that every variable receives one assignment during its
lifetime, and that Ф() functions are added at places where program flow
joins. (Id.)
3. Ananian discloses that the utilization of Ф() functions
simplifies the book-keeping for various optimizations. (Id.) Further,
Ananian discloses that by maintaining a single point of definition for every
variable, the algorithms can execute in linear time. (Id.)

IV. ANALYSIS
Claim 14
Independent claim 14 recites, in relevant parts:
[1)] each Ф() function is specified with input arguments
corresponding to type-defining occurrences of a variable that is visible
at the join point; [2)] wherein each input argument in at least one Ф()
function corresponds to a different data type assigned to the variable;
. . . and [3)] removing each Ф() function from the SSA program.

As detailed in the Findings of Fact section above, Ananian discloses
utilizing a compiler to create hardware structures for cryptographic
algorithms, such as generating and compiling VHDL code to hardware. (FF
1.) In particular, Ananian discloses an SSA form, whereby each variable
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receives one assignment. (FF 2.) Further, Ananian discloses adding Ф()
functions at places where a program flow joins. (Id.) Additionally, Ananian
discloses maintaining a single point of definition for every variable. (FF 3.)
At best, we find that Ananian’s disclosure teaches or suggests a Ф() function
that supports a definition or assignment that corresponds to at least one
variable, whereby each Ф() function is capable of being added or inserted at
places where a program flow joins. While Ananian’s Ф() function may be
capable of supporting a plurality of definitions or assignments that
correspond to both types of occurrences of a variable and different data
types assigned to the variable, such conjecture would require us to resort to
speculation, unfounded assumptions, or hindsight reconstruction. See In re
Warner, 379 F.2d 1011, 1017 (CCPA 1967). We will not resort to such
speculation or assumptions to cure the deficiencies in the factual basis to
support the Examiner’s rejection. Therefore, we find that the Examiner has
improperly relied upon Ananian’s disclosure to teach or suggest “each Ф()
function is specified with input arguments corresponding to type-defining
occurrences of a variable that is visible at the join point,” and “wherein each
input argument in at least one Ф() function corresponds to a different data
type assigned to the variable,” as recited in independent claim 14.
Moreover, Ananian’s disclosure is silent in regards to removing the
cited Ф() function from the SSA program. Accordingly, we also find that
Ananian’s disclosure falls short of teaching or suggesting “removing each
Ф() function from the SSA program,” as recited in independent claim 14.
Further, we find that Banerjee does not cure the noted deficiencies in
Ananian.
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Since Appellants have shown at least one error in the rejection of
independent claim 14, we need not reach the merits of Appellants’ other
arguments. It follows that Appellants have shown that the Examiner erred in
concluding that the combination of Banerjee and Ananian renders
independent claim 14 unpatentable.
Claims 16 through 27
Because dependent claims 16 through 27 also incorporate the
limitations discussed above, we find that Appellants have also shown error
in the Examiner’s rejection of these claims for the reasons set forth in our
discussion of independent claim 14.

V. CONCLUSION OF LAW
Appellants have shown that the Examiner erred in rejecting claims 14
and 16 through 27 as being unpatentable under 35 U.S.C. § 103(a).

VI. DECISION
We reverse the Examiner’s decision to reject claims 14 and 16
through 27.

REVERSED

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Application 10/389,368

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msc

XILINX, INC
ATTN: LEGAL DEPARTMENT
2100 LOGIC DR
SAN JOSE, CA 95124