Ex Parte Lutkemeyer

Board of Patent Appeals and Interferences

Dec 20, 2011

11029990 (B.P.A.I. Dec. 20, 2011)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte CHRISTIAN LUTKEMEYER
____________________

Appeal 2010-003920
Application 11/029,9901
Technology Center 2100
____________________

Before ALLEN R. MACDONALD, SCOTT R. BOALICK, and
JAMES R. HUGHES, Administrative Patent Judges.

HUGHES, Administrative Patent Judge.

DECISION ON APPEAL

STATEMENT OF THE CASE
Appellant appeals from the Examiner’s rejection of claims 1-27. The
Board of Patent Appeals and Interferences (BPAI) has jurisdiction under 35
U.S.C. § 6(b).
We reverse.

1 Application filed January 5, 2005. The real party in interest is Broadcom
Corp. (App. Br. 2.)
Appeal 2010-003920
Application 11/029,990

2
Appellant’s Invention
The invention at issue on appeal relates to a logic module, carry-save
accumulator, and method for implementing an integrated circuit logic
module that maximizes efficiency and minimizes energy dissipated per unit
of operation. A representative method utilizes a four input / two output
carry-save accumulator. (Spec. ¶¶ [0004], [0007]; Abstract.)2
Representative Claim
Independent claim 1 further illustrates the invention and is reproduced
below with the key disputed limitations emphasized:
1. A method of implementing signal processing
functions on an integrated circuit chip comprising:
using a minimum cell area for each of one or more cells
of one or more logic modules of said integrated circuit chip
such that an efficiency of each of said one or more logic
modules is maximized; and
using four carry-save adders in each of said one or more
logic modules.

Reference
The Examiner relies on the following reference as evidence of
unpatentability:
Letteney US 4,228,520 Oct. 14, 1980

2 Throughout our decision, we refer to Appellant’s Specification (“Spec.”);
Appeal Brief (“App. Br.”) filed May 6, 2009; and Reply Brief (“Reply Br.”)
filed November 9, 2009. We also refer to the Examiner’s Answer (“Ans.”)
mailed September 9, 2009.
Appeal 2010-003920
Application 11/029,990

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Rejections on Appeal 3
1. The Examiner rejects claims 1-6 and 10-27 under 35
U.S.C. § 102(b) as being anticipated by Letteney.
2. The Examiner rejects claims 7-9 under 35 U.S.C. § 103(a) as
being unpatentable over Letteney.

ISSUE
Based on our review of the administrative record, Appellant’s
contentions, and the Examiner’s findings and conclusions, the pivotal issue
before us is as follows:
Does the Examiner err in finding Letteney discloses or would have
taught or suggested “using a minimum cell area for each of one or more cells
of one or more logic modules of said integrated circuit chip such that an
efficiency of each of said one or more logic modules is maximized” as
recited in claim 1?

ANALYSIS
The Examiner sets forth a detailed explanation of the anticipation and
obviousness rejections in the Examiner’s Answer with respect to Appellant’s
claims (Ans. 3-10) and in particular the anticipation rejection of independent

3 The Examiner rejects claims 1-6 and 9-27 under 35 U.S.C. § 102(b) and
claims 7 and 8 under 35 U.S.C. § 103(a). (See Ans. 3, 6.) However, claim 9
is dependent on claim 7 which is rejected under 35 U.S.C. § 103(a). We find
this error harmless, but for clarity and consistency we group claims 7-9
together as rejected under § 103. The Examiner has withdrawn a rejection
of claims 10-17 under 35 U.S.C. § 112, second paragraph (Ans.2); therefore,
we will not address Appellant’s arguments (App. Br. 5-7) directed to this
rejection.
Appeal 2010-003920
Application 11/029,990

4
claim 1 (Ans. 3-4, 6-7), claim 10 (Ans. 4, 7-8), claim 18 (Ans. 3-4, 9), and
claim 24 (Ans. 5, 8). Therefore, we look to the Appellant’s Briefs to show
error in the proffered findings and conclusions. See In re Kahn, 441 F.3d
977, 985-86 (Fed. Cir. 2006) (citing In re Rouffet, 149 F.3d 1350, 1355 (Fed.
Cir. 1998)).
Arguments Concerning the Examiner’s Rejection of
Representative Claim 1 Under §102
We agree with Appellant that Letteney fails to disclose, teach, or
suggest the functionality of utilizing a minimum cell area to maximize the
efficiency of a logic module as recited by the claim for essentially the
reasons cited by Appellant. (App. Br. 9-12; Reply Br. 6-9.) Contrary to the
Examiner's assertions, Letteney’s Figure 4 does not illustrate an accumulator
that “is the same as the carry save accumulator” of Appellant’s Figure 1, and
which would inherently “have a minimum cell area, a maximum efficiency,
a minimum cell height, and a minimum energy dissipation per addition with
a minimum cell height, and a product of a time value and an area used to
implement the logic module equal a minimum value as claimed.” (Ans. 4.)
Although Letteney appears to disclose one or more logic modules
including at least four carry-save adders (see Ans. 3), we find no mention in
Letteney of the claimed functionality. Further, we do not agree that the
components identified in Letteney by the Examiner correspond to the logic
(adders) of Appellant’s claim – e.g., elements 512, 564, 520, and 524
corresponding to the second adder/compressor 104 (see Ans. 3). Thus, we
find no clear explanation, either in Letteney or the Examiner’s discussion of
the rejection, of “using a minimum cell area for each of one or more cells of
one or more logic modules of said integrated circuit chip” (i.e., minimizing
Appeal 2010-003920
Application 11/029,990

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cell area) “such that an efficiency of each of said one or more logic modules
is maximized” (i.e., while maximizing logic module efficiency) (claim 1).
Therefore, the rejection of claim 1 fails to establish a prima facie case of
anticipation.
Appellant’s independent claims 10, 18, and 24 include limitations of
similar scope. Claim 10 recites “determining a minimum cell height
associated with a first circuit area of a logic module, said first circuit area
associated with generating a maximum efficiency of said logic module, said
logic module implementing one or more digital signal processing functions.”
Claim 18 recites “four carry-save adders . . . implemented in said logic
module such that a product of a time value and an area used to implement
said logic module equals a minimum value.” Claim 24 recites “two registers
clocked by a clock having period equal to an overall processing delay
associated with said carry-save accumulator.” We find no mention in
Letteney of “determining a minimum cell height” (claim 10), “a product of a
time value and an area used to implement [a] logic module equal[ing] a
minimum value” (claim 18), or clocking “two registers . . . [using] a clock
having period equal to an overall processing delay associated with [a] carry-
save accumulator” (claim 24).
Dependent claims 2-6 (dependent on claim 1) (see note 3 (supra)), 11-
17 (dependent on claim 10), 19-23 (dependent on claim 18), and 25-27
(dependent on claim 24) stand with their respective base claims. Thus,
based on the record before us and for the reasons set forth with respect to
claim 1, we find that the Examiner erred in finding Letteney discloses the
disputed limitations recited in Appellant’s claims 2-6 and 10-27.
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Application 11/029,990

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Accordingly, we reverse the Examiner’s anticipation rejection of claims 1-6
and 10-27.
Arguments Concerning the Examiner’s Rejection of
Claims 7-9 Under §103
Dependent claims 7-9 (dependent on claim 1) (see note 3 (supra)) also
stand with claim 1. Thus, based on the record before us and for the reasons
set forth with respect to claim 1, we find that the Examiner erred in finding
Letteney would have taught or suggested the disputed limitations recited in
claims 7-9. Accordingly, we reverse the Examiner’s obviousness rejection
of these claims.

CONCLUSION OF LAW
Appellant has shown that the Examiner erred in rejecting claims 1-6
and 10-27 under 35 U.S.C. § 102(b).
Appellant has shown that the Examiner erred in rejecting claims 7-9
under 35 U.S.C. § 103(a).

DECISION
We reverse the Examiner’s rejection of claims 1-6 and 10-27 under 35
U.S.C. § 102(b).
We reverse the Examiner’s rejection of claims 7-9 under 35 U.S.C.
§ 103(a).

REVERSED

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