Ex Parte Lu et alDownload PDFPatent Trial and Appeal BoardAug 31, 201611639006 (P.T.A.B. Aug. 31, 2016) Copy Citation UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE 11/639,006 12/14/2006 42717 7590 09/02/2016 HA YNES AND BOONE, LLP IP Section 2323 Victory A venue Suite 700 Dallas, TX 75219 FIRST NAMED INVENTOR Lee-Chung Lu UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. TSMC2006-0321 4055 EXAMINER CHENG, DIANA ART UNIT PAPER NUMBER 2842 NOTIFICATION DATE DELIVERY MODE 09/02/2016 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address( es): ipdocketing@haynesboone.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Exparte LEE-CHUNG LU, CHUNG-HSING WANG, CHUN-HUI TAI, LI-CHUN TIEN, and SHUN-LI CHEN Appeal2014-007035 Application 11/639,006 Technology Center 2800 Before MARK NAGUMO, JAMES C. HOUSEL, and CHRISTOPHER C. KENNEDY, Administrative Patent Judges. HOUSEL, Administrative Patent Judge. DECISION ON APPEAL 1 Pursuant to 35 U.S.C. § 134(a), Appellants2 appeal from the Examiner's decision rejecting claims 1, 4, 5, 8, 9, 11, 12, and 14 under 1 Our decision refers to Appellants' Specification (Spec.) filed December 14, 2006, Appellants' Appeal Brief (Appeal Br.) filed October 28, 2013, the Examiner's Answer (Ans.) delivered April 10, 2014, and Appellants' Reply Brief (Reply Br.) filed June 6, 2014. 2 According to Appellants, the real party in interest is Taiwan Semiconductor Manufacturing Company, Ltd. Appeal Br. 2. Appeal2014-007035 Application 11/639,006 35 U.S.C. § 103(a) as unpatentable over AAPA3 in view of Mizuno.4 We have jurisdiction over the appeal under 35 U.S.C. § 6(b ). We REVERSE. STATEMENT OF THE CASE The invention relates to a voltage level shifter design with an Nwell coupled to a single voltage and first and second PMOS 5 transistors are formed in a single Nwell. Spec. i-fi-15-7. In this way, the inventive voltage level shifter may occupy a smaller layout area than conventional voltage level shifters in which the PMOS transistors have separate Nwells coupled to different voltages. Id. at i-fi-1 4, 19. Appellants disclose a conventional low- to-high voltage level shifter, Figure 1, reproduced below. IN 100 '-....._ ~ 4;:,~~ . . . . 106 f 104 Appellants' Figure 1, showing a schematic diagram of a conventional low-to-high voltage level shifter 3 Appellants' admitted prior art, Figure 1, and Specification i-fi-f 14--17 ("AAP A"). 4 Mizuno et al., US 2004/0012397 Al, published January 22, 2004 ("Mizuno"). 5 P-type metal oxide semiconductor. 2 Appeal2014-007035 Application 11/639,006 The conventional low-to-high voltage level shifter 100 includes PMOS transistors 110, 120, 130, NMOS6 transistors 115, 125, 135, and inverter 140. Spec. i-f 14. An input voltage IN is coupled to an inverter formed by PMOS transistor 110 and NMOS transistor 115, and an output of the inverter is coupled to the gate of NMOS transistor 125 at node 102. Id. A first positive voltage power supply VDDL is coupled to both the source 7 and the bulk of PMOS transistor 110. Id. A second positive voltage power supply VDD is coupled to the sources8 and bulks of both PMOS transistors 120, 130. Id. The drains of PMOS transistor 120 and NMOS transistor 125 are coupled at node 104, and also cross-coupled to the gate of PMOS transistor 130. Id. The drains of PMOS transistor 130 and NMOS transistor 135 are coupled at node 106, and also cross-coupled to the gate of PMOS transistor 120. Id. Inverter 140 is coupled between node 106 and an output voltage OUT, and is also coupled to VDD. Id. VDDL is for chip internal operation, while VDD at a lower voltage is for chip external operation. Id. Thus, IN equals VDDL and OUT equals VDD. Id. According to 6 N-type metal oxide semiconductor. 7 Appellants' disclose that VDDL is coupled to the drain of PMOS transistor 110 in Figure 1. Spec. i-f 14. Appellants further disclose that the embodiment of Figure 2 is exactly the same circuit construction as Figure 1, with the exception of coupling the bulk of the inverter PMOS transistor to VDD, instead of VDDL. Id. at i-f 18. Similarly, Appellants disclose the embodiment of Figure 3 to be a variant of Figure 1. However, Appellants describe in Figure 3 that VDDL is coupled to sources, not drains, of the PMOS transistors. Id. at i-f 20. As Appellants description of Figure 3 as coupling to the sources, rather than drains, of the PMOS transistors is consistent with the current claim language, we adopt this in our description of the invention. 8 See footnote 7 above. 3 Appeal2014-007035 Application 11/639,006 Appellants, a problem with this conventional voltage level shifter is that, because the bulks of PMOS transistor 110 and PMOS transistors 120, 130 are coupled to different voltages, VDDL and VDD respectively, their respective Nwells must be separated and maintained a predetermined distance, thereby occupying a larger layout area than a single Nwell layout. Id. at i-f 17. Appellants disclose a solution to this problem is to couple the bulk of PMOS transistor of the inverter (corresponding to PMOS transistor 110) to VDD, instead of VDDL. Spec. i-f 18. By doing this, each PMOS transistor is coupled to the same voltage and, therefore, may share a single Nwell. Id. at i-f 19. Claim 1, reproduced below from the Claims Appendix of the Appeal Brief, is illustrative of the subject matter on appeal. The limitations at issue are italicized. 1. A voltage level shifter with reduced layout area, comprising: an inverter including a first P-type metal-oxide- semiconductor (PMOS) transistor having a gate coupled to an input terminal, a source coupled to a first positive voltage (VDDL) and a first bulk formed within a Nwell coupled to a second positive voltage (VDD) which is higher than VDDL; a second PMOS transistor with its gate coupled to the inverter via an NMOS transistor, the second PMOS transistor has a source and a second bulk formed within said Nwell coupled to the VDD, and a drain coupled to an output node; and a third PMOS transistor having a gate coupled to the output node, a source and a third bulk formed within said Nwell coupled to the VDD, and a drain coupled to the gate of the second PMOS transistor, respectively, such that the VDDL voltage level at the input terminal is shifted to the VDD voltage level at the output node. 4 Appeal2014-007035 Application 11/639,006 ANALYSIS The Examiner finds the AAP A discloses a voltage level shifter with reduced layout area as recited in claims 1 and 9, except for coupling of the bulks of the PMOS transistors to VDD and that the PMOS transistors are all formed in the same Nwell. Ans. 2-3. However, the Examiner finds Mizuno, Figure IA, teaches an inverter where the sources of the transistors within circuit 100 are connected to vdd and vss, respectively, and the bulks of these transistors are connected to vbp and vbn, respectively. Id. at 3. Moreover, the Examiner finds vbp is positively greater than vdd, whereas vbn is negatively greater than vss. Id. The Examiner also finds Mizuno teaches the bulks of the transistors may be switched to the highest potential within the circuit to enable the circuit 100 to enter standby mode. Id. The Examiner concludes it would have been obvious to change the bulk voltage of the first PMOS of the AAP A to be of a higher voltage than that of the source voltage such that the bulks of each of the PMOS transistors are coupled to the highest potential of the circuit. Id. at 4. The Examiner also concludes that because of this arrangement, each of the PMOS transistors would be formed in the same Nwell. Id. (citing to Spec. i-f 5). The Examiner determines that the motivation for providing this arrangement would have been to decrease the power supply voltage so that a deep substrate bias can be applied between the diffusion layer and the well of the MOS transistor to a small value, reducing the leakage current with a transistor having a thin gate oxide in the off state. Id. Appellants contend that the Examiner misconstrues Mizuno' s teachings. Appeal Br. 9. In particular, Appellants assert that Mizuno teaches that the bulk voltage of the first PMOS transistor can be increased 5 Appeal2014-007035 Application 11/639,006 during standby mode to reduce power consumption and leakage current, but not during active mode. Id. at 10. In addition, Appellants argue that it would not have been obvious to have increased bulk voltage of the first PMOS transistor of the AAP A to a higher voltage during active mode because doing so would increase the substrate bias and decrease the speed of the CMOS circuit. Id. Appellants also argue that the Examiner's reliance on Specification paragraph 5 as part of the AAP A is in error, and thus the Examiner's conclusion that it would have been obvious to form each of the PMOS transistors of the AAPA in the same Nwell lacks evidentiary support. Id. at 13, 14. We agree. Although the Examiner finds Appellants' argument with regard to the operational status of the inverter to be irrelevant because Appellants claims do not recite any limitation as to operational mode (Ans. 9), we note that Mizuno' s purposes for increasing the bulk voltage, reducing power consumption and leakage current, occur only during standby mode. During active mode, Mizuno applies the same voltage to the source and bulk of the PMOS transistor to reduce substrate bias. Appeal Br. 9-10; Mizuno Fig. lB, i-f 63. The Examiner is correct that claims 1 and 9 do not expressly recite an operational mode. However, claims 1 and 9 each recite a voltage level shifter in which the bulk of the first PMOS transistor is not only at the same voltage as the second and third PMOS transistors, but these transistors share the same Nwell. As Appellants disclose, it is only possible to share the same Nwell when the voltages of these PMOS transistors are maintained at the same voltage throughout operation, regardless of standby or active mode. 6 Appeal2014-007035 Application 11/639,006 The Specification teaches a low-to-high voltage level shifter "transfers output signals from 1. OV [input signal] to 1. 8V for system operations." Spec. i-f 2. Further, Appellants' Figure 2 depicts a low-to-high voltage level shifter. Id. at ,-r 11. We note Appellants' recited voltage level shifters of claims 1 and 9 correspond to the configuration of Figure 2. In modifying Appellants' Figure 1 to arrive at Appellants' voltage level shifter of claim 1, it is necessary to couple the bulk of first PMOS transistor 110 to VDD in the same Nwell as shared by second and third PMOS transistors 120, 130. In order to do so, the voltages of each of these transistors must be the same. However, if one were to modify Appellants' Figure 1 in accordance with Mizuno to arrive at a functional device, i.e., a device capable of performing the voltage level shifting function, it would be necessary to provide separate Nwells for the PMOS transistors as the voltages of the bulk would vary depending on the operational mode-high voltage during standby; low voltage during active mode. In other words, Mizuno does not teach or suggest maintaining the bulk of the PMOS transistor at the same voltage of the other PMOS transistors during both operating modes thereby enabling the PMOS transistors to share the same Nwell. Nor has the Examiner provided any other evidence or technical reasoning that would suggest that the voltages of the PMOS transistors be maintained at the same voltage throughout operation, whether active or standby, such that they may share the same Nwell. Absent such, we are persuaded that the Examiner has not established that the voltage level shifter of claims 1 and 9 would have been obvious. Accordingly, we will not sustain the Examiner's rejection. 7 Appeal2014-007035 Application 11/639,006 DECISION Upon consideration of the record, and for the reasons given above and in the Appeal and Reply Briefs, the decision of the Examiner rejecting claims 1, 4, 5, 8, 9, 11, 12, and 14 under 35 U.S.C. § 103(a) as unpatentable over AAP A and Mizuno is reversed. REVERSED 8 Copy with citationCopy as parenthetical citation