Ex Parte Liu

Board of Patent Appeals and Interferences

May 24, 2011

10704678 (B.P.A.I. May. 24, 2011)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/704,678 11/12/2003 Yen-Fu Liu 4946-003 4442
22429 7590 05/25/2011
LOWE HAUPTMAN HAM & BERNER, LLP
1700 DIAGONAL ROAD
SUITE 300
ALEXANDRIA, VA 22314
EXAMINER
WANG, HARRIS C
ART UNIT PAPER NUMBER
2439
MAIL DATE DELIVERY MODE
05/25/2011 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________
BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________
Ex parte YEN-FU LIU
____________
Appeal 2009-011588
Application 10/704,6781
Technology Center 2400
____________

Before JEFFERY S. SMITH, ERIC B.CHEN, and MICHAEL R. ZECHER,
Administrative Patent Judges.

ZECHER, Administrative Patent Judge.

DECISION ON APPEAL

1 Filed on November 12, 2003. This application claims foreign priority to
Taiwanese application 92116632, filed on June 19, 2003. The real party in
interest is Yen-Fu Liu. (App. Br. 3.)
Appeal 2009-011588
Application 10/704,678

2
I. STATEMENT OF THE CASE
Appellant appeals under 35 U.S.C. § 134(a) (2002) from the
Examiner’s non-final rejection of claims 24-29 and 31-33. (App. Br. 3.)
Claims 1-12, 19, and20 have been cancelled. (Id.) Claims 13-18, 21, and 22
have been allowed. (Id.) Responsive to a restriction requirement, claims 34-
40 have been withdrawn from consideration.2 We have jurisdiction under 35
U.S.C. § 6(b) (2008).
We affirm-in-part.
Appellant’s Invention
Appellant invented a system for implementing a Secure Hash
Algorithm (hereinafter “SHA-1”) that offers maximum performance of the
SHA-1 utilizing minimal hardware resources. (Spec. 2, ll. 1-2.)
Illustrative Claim
Independent claim 24 further illustrates the invention as follows:
24. A system of implementing the secure hash
algorithm (SHA-1) for completing an 81-step SHA-1
computation in exactly 81 clock cycles, said system
comprising:

an addressable memory device having one data input
channel and multiple data output channels; and

a SHA-1 Logic Core coupled to both (i) the multiple data
output channels of the memory device to receive necessary data
for the 81-step SHA-1 computation and (ii) the data input

2 In the Final Rejection mailed June 20, 2008, the Examiner states that
“[c]laims 34-40 are withdrawn from consideration as being directed to a
non-elected invention.” (Fin. Rej. 2.) In the amendment entered with the
Request for Continued Examination, filed October 20, 2008, Appellant
acknowledges that claims 34-40 have been withdrawn from consideration as
being directed to a non-elected invention. (Amend. 1.)
Appeal 2009-011588
Application 10/704,678

3
channel of the memory device to return intermediate
computation values during the 81-step SHA-1 computation to
the memory device;

wherein, within one operating clock cycle of the memory
device, the data output channels of the memory device
simultaneously output different memory words from different
memory locations in accordance with a single address value at
an address input port of the memory device; and

wherein said single address value is modified internally
within said memory device to identify said different memory
locations.

Prior Art Relied Upon
The Examiner relies on the following prior art as evidence of
unpatentability:
Scheuermann US 2003/0135743 A1 July 17, 2003
(filed Mar. 5, 2002)

Rejections on Appeal
The Examiner rejects the claims on appeal as follows:
Claims 27-29 stand rejected under 35 U.S.C. § 112, first paragraph as
failing to comply with the enablement requirement.
Claims 27-29 stand rejected under 35 U.S.C. § 112, second paragraph
for failing to particularly point out and distinctly claim the subject matter
which Appellant regards as the invention.
Claims 24-26 and 31-33 stand rejected under 35 U.S.C. § 102(e) as
being anticipated by Scheuermann.
Appellant’s Contentions
1. Appellant contends that the Examiner has failed to present
evidence indicating why he or she believes that the scope of protection
Appeal 2009-011588
Application 10/704,678

4
provided by dependent claims 27-29 is not adequately enabled by the
description of the claimed invention provided in Appellant’s Specification.
(App. Br. 5-6.) Therefore, Appellant alleges that since the Examiner has
failed to meet his or her initial burden when rejecting dependent claims 27-
29 for lack of enablement, these claims comply with the enablement
requirement under 35 U.S.C. § 112, first paragraph. (Id. at 6.)
2. Appellant contends that the hardware configuration containing
multiple multiplexers and adders depicted in Appellant’s figure 3 is but one
embodiment of the claimed invention. (Id. at 5.) Consequently, Appellant
argues that the “multiple multiplexers” and “adders” recited in dependent
claims 27-29 reasonably set out and circumscribe the particular subject
matter which Appellant regards as the invention. (Id. at 6.) Therefore,
Appellant alleges that claims 27-29 are not indefinite under 35 U.S.C. § 112,
second paragraph. (Id.)
3. Appellant contends that Scheuermann does not disclose a one-
clock-cycle per sequence implementation of SHA hardware, as recited in
independent claim 24. (Id.; Reply Br. 3.) In support of this contention,
Appellant references the arguments set forth by Dr. Yu-Chee Tseng in the
declaration submitted under 37 C.F.R § 1.132, filed October 20, 2008.
(App. Br. 6.) Additionally, Appellant argues that since Scheuermann’s
figure 6b depicts SHA timing where one processing round requires 16 clock
cycles (i.e., m=16 implementation of the SHA algorithm), Scheuermann’s
design cannot be scaled to teach SHA timing where one processing round
requires 1 clock cycle (i.e., m=1 implementation of the SHA algorithm).
(Reply Br. 3-4.)

Appeal 2009-011588
Application 10/704,678

5
Examiner’s Findings and Conclusions
1. The Examiner finds that the claimed invention is directed to the
single hardware configuration depicted in Appellant’s figure 3. (Ans. 9.)
Therefore, the Examiner concludes that since dependent claims 27-29 do not
recite all the essential elements depicted in Appellant’s figure 3, these claims
fail to comply with the enablement requirement under 35 U.S.C. § 112, first
paragraph. (Id. at 9-10.)
2. The Examiner concludes that since claims 27-29 omit essential
elements depicted in Appellant’s figure 3, these claims are indefinite under
35 U.S.C. § 112, second paragraph. (Id.)
3. The Examiner finds that Scheuermann’s disclosure of an m=1
implementation of the SHA algorithm amounts to 1 clock-cycle per round
for 81 rounds. (Id. at 10-11.) Therefore, the Examiner finds that
Scheuermann teaches an 81 clock cycle SHA computation, as recited in
independent claim 24. (Id. at 11.)

II. ISSUES
1. Has Appellant shown that the Examiner erred in finding that the
claimed invention fails to comply with the enablement requirement? In
particular, this issue turns on whether the Examiner has met the initial
burden of setting forth a reasonable explanation as to why he or she believes
that the scope of protection provided by dependent claims 27-29 are not
adequately enabled by the description of the claimed invention provided in
Appellant’s Specification.
2. Has Appellant shown that the Examiner erred in concluding
that dependent claims 27-29 are indefinite? In particular, the issue turns on
Appeal 2009-011588
Application 10/704,678

6
whether an ordinarily skilled artisan, having read Appellant’s Specification,
would be apprised of the scope of:
(a) “multiple multiplexers each corresponding to one of the data
output channels…,” as recited dependent claim 27;
(b) “a number of adders each corresponding to one of the
remaining multiplexers…,” as recited in dependent claim 28.
(c) “the memory device comprises four said multiplexers and three
said adders,” as recited in dependent claim 29.
3. Has Appellant shown that the Examiner erred in finding that
Scheuermann anticipates independent claim 24? In particular, the issue
turns on whether Scheuermann describes “[a] system of implementing the
secure hash algorithm (SHA-1) for completing an 81-step SHA-1
computation in exactly 81 clock cycles,” as recited in independent claim 24.

III. FINDINGS OF FACT
The following Findings of Fact (hereinafter “FF”) are shown by a
preponderance of the evidence.
Appellant’s Specification
FF 1. Appellant’s Specification states that:
Fig. 3 is the quad-channel output memory (QCOM) architecture
block diagram….The outputs of the sixteen memory words
driving four 16-word input multiplexers (11, 12, 13, and 14).
Selecting Wt-3 is accomplished with implementing a 4-bid adder
(111) adding13 to the value of a (the address), and the output
driving the selected lines of the Wt_3 channel multiplexer (11).
Selecting Wt-8 is accomplished with implementing a 4-bit adder
(112) adding 8 to the value of a (the address), and the output
driving the select lines of the Wt_8 channel multiplexer (12).
Selecting Wt-14 is accomplished with implementing a 4-bit adder
Appeal 2009-011588
Application 10/704,678

7
(113) adding 2 to the value of a (the address), and the output
driving the select lines of the Wt_14 channel multiplexer (13).
The select lines of the Wt_16 channel multiplexer are driven
directly by the address line (a) since Wt-16 is the same as Wt-0 for
the 16-word circular queue memory. The Wt_16 channel
multiplexer (14) is also driving two 32-bit output ports: Wt_16
and dout.

(Spec. 10, ll. 17-33.)
Scheuermann
FF 2. Scheuermann discloses that the SHA-1 allows a continuum of
hardware implementations that trade performance and hardware complexity.
(¶ [0030].) In particular, Scheuermann represents the
performance/throughout by the following equation:
Throughout=(512>fmax)/(81 x m) bits per second.
(Id.) Further, Scheuermann discloses that “fmax represents the maximum
clock frequency, 81 represents 80 processing rounds plus one update round,
and m represents the number of clock periods required for each processing
round.” (Id.)
FF 3. Utilizing an implementation that has an approximate order of
magnitude increase in hardware for m=1 and fmax =100 MHz, Scheuermann
discloses achieving a performance of 79 MB/s, or 79 kilobytes per
millisecond. (¶ [0032].)

IV. ANALYSIS
35 U.S.C. § 112, First Paragraph Rejection—Enablement
The United States Patent and Trademark Office (hereinafter “PTO”)
bears the initial burden when rejecting claims for lack of enablement.
Appeal 2009-011588
Application 10/704,678

8
When rejecting a claim under the enablement requirement of
section 112, the PTO bears an initial burden of setting forth a
reasonable explanation as to why it believes that the scope of
protection provided by that claim is not adequately enabled by
the description of the invention provided in the specification of
the application; this includes, of course, providing sufficient
reasons for doubting any assertions in the specification as to the
scope of enablement. If the PTO meets this burden, the burden
then shifts to the applicant to provide suitable proofs indicating
that the specification is indeed enabling.

In re Wright, 999 F.2d 1557, 1561-62 (Fed. Cir. 1993) (citing In re
Marzocchi, 439 F.2d 220, 223-24 (CCPA 1971)).
The test for compliance with the enablement requirement of 35 U.S.C.
§ 112, first paragraph, is whether the disclosure, as filed, is sufficiently
complete to enable one of ordinary skill in the art to make and use the
claimed invention without undue experimentation. In re Wands, 858 F.2d
731, 737 (Fed. Cir. 1988). Whether undue experimentation is required is a
conclusion reached by weighing several underlying factual inquiries. Id. at
736.
We begin our analysis by noting that the Examiner does not explicitly
outline the essential elements in Appellant’s figure 3 that are allegedly
omitted from dependent claims 27-29. Moreover, we note that the Examiner
has not made a bona fide effort to weigh each of the Wands factors
individually. Therefore, we agree with Appellant that the Examiner has not
overcome the initial burden of establishing why dependent claims 27-29 are
not adequately enabled by the description of the claimed invention provided
in Appellant’s Specification. (App. Br. 5-6.) Consequently, we cannot
sustain the Examiner’s rejection of claims 27-29 under 35 U.S.C. § 112, first
paragraph as failing to comply with the enablement requirement.
Appeal 2009-011588
Application 10/704,678

9

35 U.S.C. § 112, Second Paragraph Rejection
Dependent claims 27, 28, and 29 recite, respectively: 1) “multiple
multiplexers each corresponding to one of the data output channels…;” 2) “a
number of adders each corresponding to one of the remaining
multiplexers…;” and 3) “the memory device comprises four said
multiplexers and three said adders.”
As detailed in the Findings of Fact section above, Appellant’s
Specification discloses a QCOM that includes four multiplexers that each
correspond to at least one output (i.e., multiplexers (11, 12, 13, and 14)).
(FF 1.) Appellant’s Specification also discloses that only three of the
multiplexers are directly coupled to three adders (i.e., adders (111, 112, and
113)). (Id.) Consequently, we find that an ordinarily skilled artisan,3 having
read Appellant’s Specification, would be apprised of the scope of dependent
claims 27-29. In particular, we find that an ordinarily skilled artisan would
have understood that the QCOM, or memory device, includes four

3 A claim is indefinite if, when read in light of the specification, it does not
reasonably apprise those skilled in the art of the scope of the invention.
Amgen Inc. v. Hoechst Marion Roussel, Inc., 314 F.3d 1313, 1342 (Fed. Cir.
2003) (citations omitted). In particular, our reviewing court held that the
claim as a whole must be considered to determine whether the claim
apprises one of ordinary skill in the art of its scope, and therefore serves the
notice function required by 35 U.S.C. § 112, second paragraph, by providing
clear warning to others as to what constitutes the infringement of the patent.
Solomon v. Kimberly-Clark Corp., 216 F.3d 1372, 1379 (Fed. Cir 2000)
(citations omitted). If the language of the claim is such that a person of
ordinary skill in the art could not interpret the metes and bounds of the
claims so as to understand how to avoid infringement, a rejection of the
claim under 35 U.S.C. § 112, second paragraph, is deemed appropriate.
Morton Int'l, Inc. v. Cardinal Chem. Co., 5 F.3d 1464, 1470 (Fed. Cir.
1993).
Appeal 2009-011588
Application 10/704,678

10
multiplexers, each of which correspond to one data output channel. We also
find that an ordinarily skilled artisan would have understood that the
QCOM, or memory device, includes four multiplexers and three adders,
whereby the three adders each correspond to three of the four multiplexers.
It follows that Appellant has shown that the Examiner erred in concluding
that dependent claims 27-29 are indefinite under 35 U.S.C. § 112, second
paragraph.
35 U.S.C. § 102(e) Rejection
Claim 24
Independent claim 24 recites, inter alia, “[a] system of implementing
the secure hash algorithm (SHA-1) for completing an 81-step SHA-1
computation in exactly 81 clock cycles.”
As detailed in the Findings of Fact section above, Scheuermann
discloses hardware that implements the SHA-1 algorithm. (FF 2.) In
particular, Scheuermann discloses that the performance/throughout of the
hardware is represented by the following equation:
Throughout=(512>fmax)/(81xm) bits per second.
(Id.) Scheuermann discloses that 81 represents 80 processing rounds plus
one update round and m represents the number of clock periods required for
each processing round. (Id.) Consequently, utilizing the variables m=1 and
fmax =100 MHz (FF 3), we find that Scheuermann’s disclosure describes a
SHA-1 hardware implementation that is capable of computing the SHA-1 in
81 clock periods or cycles. In other words, we find that Scheuermann’s
SHA-1 hardware is capable of implementing each sequence of the 81-
sequence SHA-1 computation in one clock cycle. Thus, we agree with the
Examiner that Scheuermann describes the disputed limitation. (Ans. 10-11.)
Appeal 2009-011588
Application 10/704,678

11
Moreover, we are not persuaded by the arguments set forth by Dr. Yu-
Chee Tseng in the declaration submitted under 37 C.F.R § 1.132, filed
October 20, 2008. Dr. Tseng states that the Scheuermann’s hardware
implementation and, in particular, the timing diagrams depicted in figures
6a-6c, are not scalable to implement the SHA in 81 clock cycles. (Decl. 2,
#5.) Rather, Dr. Tseng maintains that since each count of the “Mod 16
Counter” counts for one clock cycle, each sequence of the 81-sequence SHA
computation will take 16 clock cycles. (Id.) Therefore, Dr. Tseng contends
that Scheuermann does not disclose that the SHA hardware is capable of
implementing each sequence in one clock cycle. (Id.) We note that while a
declaration may have some probative value, the declaration may be given
little weight when considered in light of all the evidence of record in the
patent application. In re Brandstadter, 484 F.2d 1395 (CCPA 1973); see
also Manual of Patent Examining Procedure § 716.01(b)(III), Rev. 8, July
2010. Contrary to the arguments presented by Dr. Tseng, we find that the
Examiner presented sufficient evidence to warrant that Scheuermann
describes the disputed limitation. Therefore, the arguments set forth by Dr.
Tseng in the declaration do not persuade us of error in the Examiner’s
rejection. It follows that Appellant has not shown that the Examiner erred in
finding that Scheuermann anticipates independent claim 24.
Claims 25, 26, and 31-33
Appellant does not provide separate and distinct arguments for
patentability with respect to dependent claims 25, 26, and 31-33. (App.
Br 7; Reply Br. 4.) Therefore, we select independent claim 24 as
representative of the cited claims. Consequently, Appellant has not shown
error in the Examiner's rejection of dependent claims 25, 26, and 31-33 for
Appeal 2009-011588
Application 10/704,678

12
the reasons set forth in our discussion of independent claim 24. See 37
C.F.R. § 41.37(c)(1)(vii).
Appeal 2009-011588
Application 10/704,678

13
V. CONCLUSIONS OF LAW
1. Appellant has shown that the Examiner erred in finding that
claims 27-29 fail to comply with the enablement requirement under 35
U.S.C. § 112, first paragraph.
2. Appellant has shown that the Examiner erred in rejecting claims
27-29 as being indefinite under 35 U.S.C. § 112, second paragraph.
3. Appellant has not shown that the Examiner erred in rejecting
claims 24-26 and 31-33 as being anticipated under 35 U.S.C. § 102(e).

VI. DECISION
1. We reverse the Examiner’s decision to reject claims 27-29 as
failing to comply with the enablement requirement under 35 U.S.C. § 112,
first paragraph.
2. We reverse the Examiner’s decision to reject claims 27-29 as
being indefinite under 35 U.S.C. § 112, second paragraph.
3. We affirm the Examiner’s decision to reject claims 24-26 and
31-33 as being anticipated under 35 U.S.C. § 102(e).
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED-IN-PART

ELD