Ex parte LiuDownload PDFBoard of Patent Appeals and InterferencesMay 15, 200008367644 (B.P.A.I. May. 15, 2000) Copy Citation An amendment after the final rejection was filed as1 paper no. 8 and was entered in the record for the purposes of the appeal [paper no. 9]. -1- THIS OPINION WAS NOT WRITTEN FOR PUBLICATION The opinion in support of the decision being entered today (1) was not written for publication in a law journal and (2) is not binding precedent of the Board. Paper No. 12 UNITED STATES PATENT AND TRADEMARK OFFICE ________________ BEFORE THE BOARD OF PATENT APPEALS AND INTERFERENCES ________________ Ex parte JIANN LIU ________________ Appeal No. 1997-0513 Application 08/367,644 ________________ ON BRIEF ________________ Before KRASS, LALL and FRAHM, Administrative Patent Judges. LALL, Administrative Patent Judge. DECISION ON APPEAL This is a decision on appeal under 35 U.S.C. § 134 from the Examiner's final rejection of Claims 19 to 21. 1 Claims 1 to 10 have been canceled and claims 11 to 18 have Appeal No. 1997-0513 Application 08/367,644 -2- been withdrawn from consideration. The disclosed invention provides a vertical contact structure for high density integrated circuits such as DRAMs. The contact structure includes a vertical contact lying between two gates and has an insulating sleeve separating the vertical contact from a horizontal conductive layer. The conductive layer has an opening which lies over a doped region and extends partly over the two gates. The invention is further illustrated by the following claim. 19. An integrated circuit contact structure, comprising: (a) first and second insulated gates at the surface of a substrate; (b) sidewall insulators on said first and second gates, said sidewall insulators made of a first material; (c) a doped region in said substrate at said surface and located between said gates; (d) a conductive layer spaced from and overlying said gates, said conductive layer having an opening over said doped region and extending over a portion of each of said gates; and (e) a contact extending from said doped region through said opening to a higer [sic, higher] level than said conductive layer, with the portion of said contact in said opening not extending over any portion of said gates. Appeal No. 1997-0513 Application 08/367,644 -3- The Examiner’s rejection relies on the following references: Ishijima 4,985,718 Jan. 15, 1991 Gotou 5,126,810 Jun. 30, 1992 Claims 19 through 21 stand rejected under 35 U.S.C. § 102 as being anticipated by Ishijima or Gotou. Rather than repeat the arguments of Appellant and the Examiner, we make reference to the brief and the answer for the respective details thereof. OPINION We have considered the rejections advanced by the Examiner and the supporting arguments. We have, likewise, reviewed the Appellant’s arguments set forth in the brief. It is our view that claims 19 to 21 are not anticipated by Ishijima or Gotou. Accordingly, we reverse. In our analysis, we are guided by the requirements of anticipation under 35 U.S.C. § 102. Anticipation under 35 U.S.C. § 102 is established only when a single prior art reference discloses, either expressly or under the principles of inherency, each and every element of a claimed invention. Appeal No. 1997-0513 Application 08/367,644 -4- See RCA Corp. v. Applied Digital Data Sys., Inc., 730 F.2d 1440, 1444, 221 USPQ 385, 388 (Fed. Cir. 1984). Claims 19 through 21 These claims are rejected as being anticipated by Ishijima or Gotou. There is no dispute as to what Ishijima or Gotou discloses. The crux of the issue is the interpretation of the claims. We consider independent claim 19. The claim recites the limitation "a conductive layer spaced from and overlying said gates, said layer having an opening over said doped region and extending over a portion of each of said gates." Appellant argues [brief, page 3] that neither Ishijima nor Gotou shows a conductive layer which has an opening which overlies the doped region and extends over a portion of each of the gates. The Examiner vehemently disagrees with this interpretation of the claimed recitation. The Examiner asserts [answer, pages 5 to 7] that the above claimed limitation “does not require 'the opening in the conductive layer to extend over the gates'" [id. 5]. Appeal No. 1997-0513 Application 08/367,644 -5- We understand the Examiner’s position, based on his interpretation of the claim. However, such an interpretation of the claimed limitation is one which would result from looking at the claim in vacuum. We find it clear that undercuts 34 and 36 in the conducting layer 28 (figs. 3 and 4 of the specification) are provided to extend the opening 32 over a part of the gates 14 and 16, so that insulation 40 provides an extra insulating buffer between the contact 42 and the conductive layer 28. Whereas we agree with the Examiner that the claim would have been better drafted had Appellant employed a better phrase to bring out the inventive feature that it is the opening, and not the conductive layer, which extends in part over the gates, we here construe the claim in light of the specification. For example, the specification states that “[a]nother important technical advantage of the present invention is the fact that the conducting layer is undercut at the contact hole, thereby allowing for sufficient insulation to be disposed between the contact hole and the conducting layer.” [Page 3, lines 27 to 31]. We interpret the claimed limitation as requiring the opening in the conductive layer to extend from the contact hole over a part Appeal No. 1997-0513 Application 08/367,644 -6- of the gates. With this interpretation of the claim, we agree with Appellant that neither Ishijima nor Gotou shows this feature. Therefore, we do not sustain the anticipation rejection of claim 19 and its dependent claims 20 and 21. REVERSED ERROL A. KRASS ) Administrative Patent Judge ) ) ) ) PARSHOTAM S. LALL ) BOARD OF PATENT Administrative Patent Judge ) APPEALS AND ) INTERFERENCES ) ) ERIC FRAHM ) Appeal No. 1997-0513 Application 08/367,644 -7- Administrative Patent Judge ) psl/ki Douglas A. Sorensen Texas Instruments Incorporated P. O. Box 655474 MS 219 Dallas, TX 75265 Copy with citationCopy as parenthetical citation