Ex Parte Lindsay et al

Patent Trial and Appeal Board

Oct 25, 2012

10887123 (P.T.A.B. Oct. 25, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte STEVEN B. LINDSAY and GARY ALVSTAD
____________________

Appeal 2010-003252
Application 10/887,123
Technology Center 2400
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Before ALLEN R. MacDONALD, ERIC S. FRAHM, and
TREVOR M. JEFFERSON, Administrative Patent Judges.

FRAHM, Administrative Patent Judge.

DECISION ON APPEAL

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STATEMENT OF THE CASE1
Introduction
Appellants appeal under 35 U.S.C. § 134(a) from a final rejection of
claims 1-24, all the claims pending in the application. We have jurisdiction
under 35 U.S.C. § 6(b). We affirm.
Appellants’ Disclosed Invention
Appellants disclose a high speed networking hardware that includes a
dual port Ethernet controller chip (Spec. ¶ [0004]).
Exemplary Claims
An understanding of the invention can be derived from a reading of
exemplary claims 1 and 11, which are reproduced below with emphases
added:
1. A method for processing network data, the method comprising:
receiving data by a first Ethernet controller integrated within a
chip;
receiving data by a second Ethernet controller integrated within
said chip; and
arbitrating which one of said first Ethernet controller and said
second Ethernet controller can transfer data over a single bus interface
integrated within said chip.

11. A dual port Ethernet controller; comprising:
a bus interface;
a first Ethernet controller coupled to said bus interface; and
a second Ethernet controller coupled to said bus interface, said

1 Our decision will make reference to Appellant’s Appeal Brief (“Br.,” filed
July 13, 2009) and the Examiner’s Answer (“Ans.,” mailed October 14,
2009). The Reply Brief, filed December 1, 2009, is not before us because it
was denied entry as will be discussed infra.
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bus interface, said first Ethernet controller and said second Ethernet
controller integrated within a single chip.

The Examiner’s Rejections
(1) The Examiner rejected claims 1 and 5-12 under 35 U.S.C. § 103(a)
as being unpatentable over the combination of Wong (US 6,901,072 B1) and
Nanduri (US 7,251,249 B2). Ans. 3-11.
(2) The Examiner rejected claims 2-4 under 35 U.S.C. § 103(a) as
being unpatentable over the combination of Wong, Nanduri, and Stewart
(US 4,858,173 A). Ans. 14-17.
(3) The Examiner rejected claim 13 under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Wong, Nanduri, and Tota (US
6,539,488 B1). Ans. 17-18.
(4) The Examiner rejected claims 14 and 15 under 35 U.S.C. § 103(a)
as being unpatentable over the combination of Wong, Nanduri, Tota, and
Harari (US 2007/0016704 A1). Ans. 18-19.
(5) The Examiner rejected claim 16 under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Wong, Nanduri, Tota, Harari, and
Colton (US 2005/0089027 A1). Ans. 20.
(6) The Examiner rejected claim 17 under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Wong, Nanduri, and Salmonsen (US
2007/0005334 A1). Ans. 21-22.
(7) The Examiner rejected claim 18 under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Wong, Nanduri, Salmonsen, and
Wynn (US 6,275,499 B1). Ans. 26-28.
(8) The Examiner rejected claim 19 under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Wong, Nanduri, Salmonsen, and
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Adams (US 5,852,609). Ans. 22-24.
(9) The Examiner rejected claim 20 under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Wong, Nanduri, and Fore (US
2004/0193303 A1). Ans. 24-25.
(10) The Examiner rejected claim 21 under 35 U.S.C. § 103(a) as
being unpatentable over the combination of Wong, Nanduri, and Wang (US
2007/0153822 A1). Ans. 25-26.
(11) The Examiner rejected claim 22 under 35 U.S.C. § 103(a) as
being unpatentable over the combination of Wong, Nanduri, Shin (US
6,321,340 B1), and Lin (US 6,564,161 B1). Ans. 11-13.
(12) The Examiner rejected claims 23 and 24 under 35 U.S.C.
§ 103(a) as being unpatentable over the combination of Wong, Nanduri, and
Nogradi (US 5,974,518 A). Ans. 13-14.
Appellants’ Contentions
Appellants contend (Br. 7-24) that the Examiner erred in rejecting
claims 1-24 under U.S.C. § 103(a) as being unpatentable over the various
combinations of references for numerous reasons, including:
(1) Wong and Nanduri, as combined, do not teach or suggest a first
Ethernet controller and a second Ethernet controller integrated within the
same chip, as recited in claims 1 and 11 (Br. 7-16);2

2 Because Appellants’ arguments for claims 1 and 11 are substantively the
same (compare Br. 7-11 with Br. 11-14), claims 1 and 11 require the same
substantive limitations (namely, first and second Ethernet controllers
integrated within the same chip), and the rejections for claims 1 and 11 are
substantively the same (compare Ans. 3-5 with Ans. 6-8), we group
independent claim 11 with independent claim 1. Dependent claims 5-10 and
12 are argued as patentable for the reasons of claim 1 (Br. 11 and 14-15) and
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(2) Wong, Nanduri, and Stewart, as combined, do not teach or
suggest “successful arbitration,” as recited in claim 2 or transferring the
received data from the Ethernet controller to the integrated single bus
interface, as required by claim 3 (Br. 17-19);3 and
(3) Wong, Nanduri, and Salmonsen, as combined, do not teach or
suggest an Ethernet transceiver, as recited in claim 17 (Br. 20-22).
Appellants also argue that claims 13-16 and 18-24, rejected under
various different combinations of references, are patentable because the
additional references do not overcome the deficiencies argued with respect
to independent claims 1 and 11 rejected over the combination of Wong and
Nanduri (Br. 16-17, 20, and 23-24).
Reply Brief
A reply brief shall not include any new or non-admitted affidavits or
other Evidence. 37 C.F.R. § 41.41(b)(1). If a reply is non-compliant with
Rule 41.41, then the primary examiner must notify Appellants and provide a
reason for non-entry. MPEP 1208; see 37 C.F.R. § 41.43.
Appellants filed a Reply Brief on December 1, 2009. In an Office
communication mailed January 13, 2010, the Primary Examiner notified
Appellants that the Reply Brief was denied entry for non-compliance with
Rule 41.41, reasoning that the Reply Brief included new evidence.

claim 11 (Br. 16), respectively, which are not considered arguments for
separate patentability. We select claim 1 as representative of the group of
claims 1 and 5-12. 37 C.F.R. § 41.37(c)(1)(vii).
3 Appellants argue that claim 4, which further depends from claim 3, is
patentable because it depends from claim 1 (Br. 19), which is not an
argument for separate patentability. Therefore, we group claim 4 with
claims 2 and 3.
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Appellants filed a response on February 11, 2010 disagreeing with the denial
of entry and requesting consideration of the Reply Brief.
The Primary Examiner properly notified Appellants that the Reply
Brief was denied entry as being non-compliant with Rule 41.41 because it
included new evidence. Therefore, we decline to consider the Reply Brief.
Issues on Appeal
(1) Did the Examiner err in rejecting claims 1, 4-16, and 18-24
because Wong and Nanduri, as combined, do not teach or suggest a first
Ethernet controller and a second Ethernet controller integrated within the
same chip, as recited in claims 1 and 11;
(2) Did the Examiner err in rejecting claims 2 and 3 because Wong,
Nanduri, and Stewart, as combined, do not teach or suggest “successful
arbitration,” as recited in claim 2 or transferring the received data from the
Ethernet controller to the integrated single bus interface, as required by
claim 3; and
(3) Did the Examiner err in rejecting claim 17 because Wong,
Nanduri, and Salmonsen, as combined, do not teach or suggest an Ethernet
transceiver, as recited in claim 17?

ANALYSIS
We have reviewed the Examiner’s rejections in light of Appellants’
contention in the Appeal Brief (Br. 7-24) that the Examiner has erred.
We disagree with the Appellants’ conclusions. We adopt as our own
(1) the findings and reasons set forth by the Examiner in the action from
which this appeal is taken and (2) the reasons set forth by the Examiner in
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the Examiner’s Answer in response to the Appellants’ Appeal Brief (Ans. 3-
55).
Specifically, with regard to claims 1 and 11, we agree with the
Examiner’s findings and conclusions, including that (i) because Wong
discloses media access controllers 904a and 904b for handling and
controlling Ethernet packets, Wong teaches or suggests Ethernet controllers;
(ii) Wong discloses a transmission manager 914 that acts as an arbitrator;
and (iii) Wong’s backplane 916 including the two sided arrow connecting
914 and 916 shown in Figure 9 is a single bus interface (Ans. 28-41).
With regard to claims 2 and 3, we agree with the Examiner (Ans. 43-
48) that Stewart (column 6, lines 41-45) teaches or suggests arbitration
acknowledgement being received for bus access.
Integrating two elements into one is merely a matter of engineering
choice and would be obvious to one of ordinary skill in the art. In re
Larson, 340 F.2d 965, 968 (CCPA 1965). The rearrangement of parts in a
device is obvious and unpatentable where shifting the positions of the parts
would not have modified the operation of the device. In re Kuhle, 526 F.2d
553, 555 (CCPA 1975); In re Japikse, 181 F.2d 1019, 1032 (CCPA 1950).
With regard to claim 17, we agree with the Examiner (Ans. 50-52)
that it would have been obvious to one of ordinary skill in the art to integrate
the PHY transceiver 300 and the MAC (i.e., Ethernet) controller 302 shown
in Wong’s Figure 3, because the integration and/or rearrangement of parts is
merely a matter of engineering choice and would be obvious to one of
ordinary skill in the art; especially when shifting the positions of the parts
would not have modified the operation of the device. Larson, 340 F.2d at
968; Kuhle, 526 F.2d at 555; Japikse, 181 F.2d at 1032.
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We consider it an obvious expedient to the artisan to integrate
circuitry, such as the MAC (i.e., Ethernet) controller 302 and transceiver 300
of Wong, in a data routing and transmission system configuration (e.g.,
Wong’s transmission and reception processors shown in Figure 3 and/or the
system architecture shown in Figure 9). It would have been obvious to one
of ordinary skill in the art looking at the teachings and suggestions of Wong
to provide Ethernet control and transceiving in one device in order to
simplify and reduce costs in the processors shown in Figure 3, and thus
provide increased capabilities in either of the MAC (i.e., Ethernet)
controllers 904a and/or 904b shown in the printed circuit board of Figure 9.

CONCLUSIONS
(1) The Examiner did not err in rejecting:
(a) claims 1 and 5-12 under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Wong and Nanduri because
Wong and Nanduri, as combined teach or suggest a first Ethernet
controller and a second Ethernet controller integrated within the same
chip, as recited in claims 1 and 11;
(b) claims 2-4 under 35 U.S.C. § 103(a) as being unpatentable
over the combination of Wong, Nanduri, and Stewart because Wong,
Nanduri, and Stewart, as combined, teach or suggest successful
arbitration, as recited in claim 2, and transferring the received data
from the Ethernet controller to the integrated single bus interface, as
required by claim 3;
(c) claim 17 under 35 U.S.C. § 103(a) as being unpatentable
over the combination of Wong, Nanduri, and Salmonsen because
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Wong, Nanduri, and Salmonsen, as combined, teach or suggest an
Ethernet transceiver; and
(d) claims 13-16 and 18-24 under 35 U.S.C. § 103(a) as being
unpatentable over Wong and Nanduri in view of the various different
combinations of tertiary references as applied for the reasons
discussed in connection with claim 11.
(2) Claims 1-24 are not patentable.

DECISION
The Examiner’s rejections of claims 1-24 are affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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