Ex Parte Lindholm et al

Patent Trial and Appeal Board

Mar 25, 2014

11458633 (P.T.A.B. Mar. 25, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
_____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
_____________

Ex parte JOHN ERIK LINDHOLM, BRETT W. COON,
STUART F. OBERMAN, MING Y. SIU,
and MATTHEW P. GERLACH
_____________

Appeal 2011-008629
Application 11/458,633
Technology Center 2600
______________

Before MARC S. HOFF, DAVID M. KOHUT, and
IRVIN E. BRANCH, Administrative Patent Judges.

KOHUT, Administrative Patent Judge.

DECISION ON APPEAL

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This is a decision on appeal under 35 U.S.C. § 134(a) of the Final
Rejection of claims 1-4, 6-9, 11, 12, 19, 20, 22, 23, and 25.1 We have
jurisdiction under 35 U.S.C. § 6(b).
We affirm-in-part the Examiner’s rejection of these claims.

INVENTION
The invention is directed to multithreaded processing of graphics data
in a programmable graphics processor. Spec. ¶ [0002]. Claims 1 and 2 are
illustrative of the invention and are reproduced below:
1. A processing unit comprising:
a first input section for receiving pixel data;
a second input section for receiving vertex data;
an execution pipeline coupled to the first input section
and the second input section, wherein the execution pipeline
includes a plurality of parallel data execution paths through
which a group of pixel data or vertex data is processed in
parallel;
a first output section coupled to the execution pipeline for
storing pixel data processed by the execution pipeline; and
a second output section coupled to the execution pipeline
for storing vertex data processed by the execution pipeline.

2. The processing unit according to claim 1, further comprising
another execution pipeline coupled to the first input section, the
second input section, the first output section and the second
output section.

REFERENCES
Boyd '325 US 6,819,325 B2 Nov. 16, 2004
Boyd '330 US 2005/0122330 A1 June 9, 2005

1 Claims 5, 13-18, 21, and 27 were previously cancelled. Claims 10, 24, and
26 were indicated to include allowable subject matter and objected to as
being dependent upon a rejected base claim. Ans. 7.
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REJECTIONS AT ISSUE
Claims 1-4, 6-9, 19, 22, and 23 are rejected under 35 U.S.C. § 102(e)
as being anticipated by Boyd '330. Ans. 3-5.
Claims 11, 12, 20, and 25 are rejected under 35 U.S.C. § 103(a) as
being unpatentable over the combination of Boyd '330 and Boyd '325.
Ans. 5-7.

ISSUES
Did the Examiner err in finding that Boyd '330 discloses an execution
pipeline coupled to first input and output sections for pixel data and second
input and output sections for vertex data, as required by independent claims
1 and 19?
Did the Examiner err in finding that Boyd '330 discloses another
execution pipeline coupled to the first input and output sections for pixel
data and the second input and output sections for vertex data, as required by
claim 2?

ANALYSIS
Claim 12
Appellants initially argue that Boyd '330 fails to describe an execution
pipeline that is coupled with first input and output sections for pixel data and
second input and output sections for vertex data. App. Br. 12. Specifically,
Appellants contend that Boyd '330 describes a vertex shader and a pixel

2 We select claim 1 as representative of the group comprising claims 1, 3, 4,
6-9, 11, 12, 19, 20, 22, 23, and 25 since Appellants do not argue any of the
other claims with particularity. 37 C.F.R. § 41.37(c)(1)(vii).
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shader, each having a separate and distinct set of execution pipes and only
having a single input section and a single output section. App. Br. 12-13.
We disagree.
The Examiner finds that Figure 11B of Boyd '330 discloses an
execution pipeline that includes a vertex shader, setup engine, and pixel
shader. Ans. 8 (citing Fig. 11B). In addition, the Examiner finds that the
execution pipeline is coupled to first input and output sections for pixel data
as shown in Figure 11A and second input and output sections for vertex data
as shown in Figure 8A. Id. We agree with the Examiner’s findings because,
as shown in the cited figures and in paragraphs [0025] and [0032], Boyd
'330’s execution pipeline provides the ability to process, through first and
second input and output sections, either pixel data or vertex data in parallel.
Next, Appellants argue that Boyd '330 does not describe where the
execution pipes of the vertex shader and the pixel shader process both vertex
data and pixel data. App. Br. 12-13. However, as indicated above, we agree
with the Examiner (Ans. 4, 8) that the figures show Boyd '330 processes
both vertex data and pixel data.
Further, Appellants contend that the graphics processing pipeline of
Boyd '330 is different than the claimed execution pipeline. App. Br. 13. To
illustrate this difference, Appellants refer to examples in their Specification
that refer to an execution pipeline having multiple multi-threaded processing
units, wherein the vertex data and pixel data are processed by the same
hardware unit. Id. (citing Figs. 1-3). First, we note that these contentions
are not commensurate in scope with the claim, as the claim does not require
the different types of data to be processed by the same hardware unit.
Second, Appellants’ Specification does not specifically define an “execution
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pipeline,” but rather provide examples of execution pipelines. As such, the
Examiner’s interpretation of an “execution pipeline” as including multiple
processing units connected to each other (Ans. 8) is both reasonable and
consistent with Appellants’ Specification.
Appellants additionally refer to U.S. Patent No. 6,247,119 to attempt
to show that one of ordinary skill in the art would interpret the claimed
execution pipeline as “separat[ing] the operations for executing an
instruction into a plurality of successive stages.” Reply Br. 5-6. We do not
find this evidence to be persuasive as the '119 Patent, again, only provides
an example of an execution pipeline, not a specific definition for one.
Finally, Appellants argue that even if Boyd '330’s vertex shader, setup
engine, and pixel shader are considered an execution pipeline, the inputs and
outputs for pixel data and vertex data are not “coupled to” the execution
pipeline because the inputs and outputs referred to by the Examiner are
internal to the execution pipeline, not “coupled to” the execution pipeline.
Rep. Br. 5-6. We disagree.
The broad term “coupled to” does not preclude an internal connection.
Thus, we agree with the Examiner (Ans. 8) that the inputs and outputs for
pixel data and vertex data are “coupled to” the execution pipeline because
they are connected to the execution pipeline.
For the reasons stated supra, we sustain the Examiner’s rejection of
claims 1, 3, 4, 6-9, 11, 12, 19, 20, 22, 23, and 25.

Claim 2
Claim 2 requires “another execution pipeline” coupled to the first
input and output for pixel data and the second input and output for vertex
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data. The Examiner finds that Boyd '330 discloses this limitation by
referring to “setup engine in Figs. 5A and 11B.” Ans. 4. Appellants argue
that the Examiner’s finding is in error because the claims require more than
one pipeline, as indicated by claim 2’s recitation of “another execution
pipeline.” App. Br. 14. Appellants argue that the Examiner’s finding in
Figures 5A and 11B only describes one execution pipeline. App. Br. 14.
We agree with Appellants because the Examiner has merely referred to the
same execution pipeline that the Examiner found to be the first execution
pipeline of claim 1 (Ans. 3-4) without showing, or explaining in a sufficient
manner, where Boyd '330 describes “another,” i.e., a second execution
pipeline. Thus, for the reasons stated supra, we cannot sustain the
Examiner’s rejection of claim 2.

CONCLUSION
The Examiner did not err in finding that Boyd '330 discloses an
execution pipeline coupled to first input and output sections for pixel data
and second input and output sections for vertex data, as required by
independent claims 1 and 19.
The Examiner erred in finding that Boyd '330 discloses another
execution pipeline coupled to the first input and output sections for pixel
data and the second input and output sections for vertex data, as required by
claim 2.

SUMMARY
The Examiner’s decision to reject claims 1, 3, 4, 6-9, 11, 12, 19, 20,
22, 23, and 25 is affirmed.
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The Examiner’s decision to reject claim 2 is reversed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED-IN-PART

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