Ex Parte Lin et al

Patent Trial and Appeal Board

Oct 23, 2017

13972766 (P.T.A.B. Oct. 23, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
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APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/972,766 08/21/2013 Shao C. Lin AVC13-1001US 1483
124903 7590 10/25/2017
Park, Vaughan, Fleming & Dowler LLP — Yao Group
2800 Fifth Street, Suite 110
Davis, CA 95618
EXAMINER
LU, ZHIYU
ART UNIT PAPER NUMBER
2649
NOTIFICATION DATE DELIVERY MODE
10/25/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
syadmin@parklegal.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte SHAO C. LIN, CHUNG-HSING CHANG,
and SHIH HSIUNG MO
Appeal 2017-005903
Application 13/972,766
Technology Center 2600
Before ERIC S. FRAHM, JOHN A. EVANS, and
STEVEN M. AMUNDSON, Administrative Patent Judges.
AMUNDSON, Administrative Patent Judge.
DECISION ON APPEAL
Appellants1 seek our review under 35 U.S.C. § 134(a) from a final
rejection of claims 1—14, i.e., all pending claims. We have jurisdiction under
35 U.S.C. § 6(b).
We affirm.
1 Appellants identify the real party in interest as Aviacomm Inc. App. Br. 4.
Appeal 2017-005903
Application 13/972,766
STATEMENT OF THE CASE
The Invention
According to the Specification, the invention “relates generally to a
radio frequency (RF) front-end for a wireless communication system” and
more specifically “relates to an interface based on a programmable logic
device for controlling various RF front-end components.” Spec. IF2 The
Specification explains that a “programmable logic chip” (1) receives a
“command” from a “baseband chip” via a “first interface”; (2) “identifies the
RF front-end component based on an address indicated by the command”;
and (3) “sends a control signal included in the command to the identified RF
front-end component” via a “second interface.” Abstract. The Specification
also explains that “the term ‘RF front-end component’ or ‘RF front-end
module’ can refer to any component or module between the antenna and the
digital baseband system in a radio.” Spec. 118.
Exemplary Claim
Independent claim 1 exemplifies the claims at issue and reads as
follows:
1. A method for controlling one or more RF front-end
components, comprising:
receiving, by a programmable logic chip from a baseband
chip, a command, wherein the programmable logic chip is
coupled to the baseband chip via a first interface, and wherein
the programmable logic chip has a second interface comprising
2 This decision uses the following abbreviations: “Spec.” for the
Specification, filed August 21, 2013; “Final Act.” for the Final Office
Action, mailed January 11, 2016; “App. Br.” for the Appeal Brief, filed
June 13, 2016; “Ans.” for the Examiner’s Answer, mailed December 23,
2016; and “Reply Br.” for the Reply Brief, filed February 22, 2017.
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a plurality of I/O pins coupled to the one or more RF front-end
components;
identifying, from the plurality of I/O pins of the second
interface, one or more I/O pins that are a subset of the second
interface and are mapped to an RF front-end component based
on an address for the RF front-end component indicated by the
command; and
sending a control signal included in the command to the
corresponding RF front-end component via the identified I/O
pins.
App. Br. 29 (Claims App.).
The Prior Art Supporting the Rejection on Appeal
As evidence of unpatentability, the Examiner relies on the following
prior art:
Bhanji et al. (“Bhanji”) US 2006/0199622 A1 Sept. 7, 2006
Roller et al. (“Roller”) US 2009/0061787 Al Mar. 5, 2009
Devison US 2010/0124260 Al May 20, 2010
The Rejection on Appeal
Claims 1—14 stand rejected under 35 U.S.C. § 103(a) as unpatentable
over Roller, Devison, and Bhanji. Final Act. 3—7.
ANALYSIS
We have reviewed the rejection of claims 1—14 in light of Appellants’
arguments that the Examiner erred. For the reasons explained below, we
disagree with Appellants’ assertions regarding Examiner error. We adopt
the Examiner’s findings and reasoning in the Final Office Action (Final
Act. 2—7) and Answer (Ans. 2—9). We add the following to address and
emphasize specific findings and arguments.
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The § 103(a) Rejection of Claims 1—14
The “Identifying” and “Sending” Limitations
Appellants argue that the Examiner erred in rejecting independent
claims 1 and 8 because “there is nothing . . . either expressly or inherently”
in the references that discloses the “identifying” and “sending” limitations in
claim 1 and comparable limitations in claim 8. See App. Br. 15—18, 20-24,
28; Reply Br. 9—11, 13—14. In arguing patentability, Appellants repeatedly
(1) identify a disclosure the Examiner cites, (2) assert that the identified
disclosure “is not the same” as a disputed limitation, and (3) fail to explain
any differences. See, e.g., App. Br. 20-24, 26; Reply Br. 9-11, 13.
As an example, Appellants contend that (1) Roller “merely discloses
transmitting an address via a parallel bus or a serial bus” and
(2) “transmitting an address via a parallel or serial bus is not the same as”
the disputed “identifying” and “sending” limitations. App. Br. 19-20; Reply
Br. 10. As another example, Appellants contend that Devison’s disclosure
concerning “issuing a memory address which corresponds to pre-stored data
in the addressed memory location is not the same as” the disputed
“identifying” and “sending” limitations. App. Br. 21; Reply Br. 11. Asa
further example, Appellants assert that Bhanji’s disclosure concerning
“mapping pins to a memory location (e.g., register space) is not the same as”
the disputed “identifying” limitation. App. Br. 24.
Appellants’ arguments do not persuade us of Examiner error because,
as the Examiner points out, an appellant cannot establish nonobviousness by
attacking the references individually where a rejection rests on a
combination of references. See In re Merck & Co., 800 F.2d 1091, 1097
(Fed. Cir. 1986); see also Final Act. 2; Ans. 9. “[T]he test for combining
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references is not what the individual references themselves suggest but
rather what the combination of disclosures taken as a whole would suggest
to one of ordinary skill in the art.” In re McLaughlin, 443 F.2d 1392, 1395
(CCPA 1971). Appellants do not address “what the combination of
disclosures taken as a whole would suggest to one of ordinary skill in the
art” and, therefore, have not demonstrated Examiner error. App. Br. 14—24;
Reply Br. 9—14.
Moreover, Roller does not “merely disclose[] transmitting an address
via a parallel bus or a serial bus.” See App. Br. 19. Instead, Roller discloses
that a baseband device sends a “telegram” to a controller device via an
interface. Roller H 39-40, 45, 47-48. A telegram may include a “control
packet comprising a control command requesting a specific mode of
operation” for the front-end sub-circuits. Id. H 40, 48. The front-end sub­
circuits “may comprise one or more adjustable parameters in order to change
the signal processing behavior of the respective sub-circuit,” e.g.,
components including a low-noise amplifier (LNA) and a power amplifier
(PA). Id. 22, 25—26, 46, 69, Fig. 2. The controller device processes a
control packet from the baseband device and determines the “required
configuration patterns” corresponding to the desired mode of operation for
the front-end sub-circuits. Id. H 36, 45, 48.
To set the desired mode of operation, the controller device “loads one
or more configuration patterns out of the memory and buffers them in one or
more registers” in the controller device. Roller H 36, 45, 48, Figs. 2—3.
The controller device uses an index or address to access a configuration
pattern in the memory. Id. H 46, 48, 70. “[T]he index may comprise a
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specific address of the memory in which the corresponding configuration
pattern is stored.” Id. 170.
Koller also discloses that a trigger signal causes a register in the
controller device to provide an appropriate “configuration pattern
comprising a plurality of bits in parallel” to “control pins” for the front-end
sub-circuits. Koller H 36, 46, 50-51, Figs. 2—3. Figure 2 depicts the
“control pins” coupled to the front-end sub-circuits. Koller alternately refers
to the “control pins” as “output pins,” an “output interface,” and a “control
interface.” Id. H 8, 50—51. Koller explains that “[t]he configuration pattern
provided at the control interface configures the sub-circuits ... in
accordance with a requirement set forth by the control packet or the
information therein.” Id. ^ 8. The Specification describes an arrangement
like Koller’s. See, e.g., Spec. H 25—26.
Consequently, Koller teaches or suggests a baseband chip sending a
command containing information corresponding to an index or address for a
configuration pattern stored in a memory and providing the configuration
pattern to interface pins mapped to RF front-end components. See Final
Act. 3^1; Ans. 2-3, 7; Koller H 8, 36, 39-40, 45^18, 50-51, 70, Figs. 2-3.
The different configuration patterns identify various subsets of the interface
pins through different logic-high/logic-low combinations corresponding to
control signals for selected RF front-end components. See Ans. 7; Koller
11 5—9, 36, 46, 50-51, Figs. 2—3. The Specification explains that a “simple
binary signal for ‘on’ and ‘off” may constitute a “control signal.” Spec.
125.
In addition, Devison discloses a memory subsystem in an RF
transceiver receiving a baseband command for controlling RF front-end
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components. Devison H 33—35, 46-47, Fig. 3, Fig. 6. “[T]he baseband
command can be an address to access a memory location of the memory
subsystem.” Id. 133; see id. H 12, 14, 32. The RF front-end components
include power amplifiers 322 and 324 and low-noise amplifiers 326 and 328.
Id. 148, Fig. 6. The memory subsystem “stores bit patterns” such that “each
bit pattern corresponds to a particular control configuration for a specific
radio operation.” Id. 129. A “control device,” e.g., a “baseband processor,”
provides an “address corresponding to the desired functional operation of the
peripheral components,” and the memory subsystem “uses the address to
output the appropriate bit pattern,” e.g., “in parallel to statically control
individual control lines.” Id. H 29, 32. Figure 6 depicts a “parallel bus
control scheme” with a “plurality of signal lines” attached to eight output
pins for direct amplifier control. Id. H 46-47, Fig. 6. Four of the output
pins provide enable signals El, E2, E3, and E4 used to enable the respective
amplifiers 322, 324, 326, and 328. Id. 148. Thus, each of those four output
pins is mapped to a particular amplifier. Id. 148, Fig. 6. For example, the
memory subsystem’s upper output pin providing signal El is mapped to the
power amplifier 322, while the memory subsystem’s lower output pin
providing signal E4 is mapped to the low-noise amplifier 328. Id. Fig. 6.
When the memory subsystem receives from the control device a
memory address corresponding to a desired operation, the memory
subsystem uses that address to access the memory location containing the
pre-stored bit pattern for implementing the desired operation. Devison
1147, 49. The pre-stored bit patterns have bit positions mapped to specific
output pins, e.g., to enable one amplifier and disable the other amplifiers. Id.
1149-51, Fig. 8.
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Accordingly, Devison teaches or suggests receiving a baseband
command including a memory address, identifying based on the memory
address an output pin mapped to an RF front-end component, and sending a
control signal to the RF front-end component associated with the memory
address. See Final Act. 4; Ans. 3—4, 7—9; Devison || 12, 14, 29, 32—36, 46—
51, Fig. 3, Fig. 6.
The Examiner relies on Bhanji for teaching or suggesting a
programmable logic chip including a particular type of integrated circuit,
i.e., a field-programmable gate array, used in a wireless transceiver. See
Final Act. 5—6; Ans. 4—5, 9. Because the Examiner does not rely on Bhanji
for the disputed limitations, Appellants’ arguments regarding Bhanji (as
failing to disclose the disputed limitations) do not respond to the rejection.
Appellants contend that Roller’s controller device “transmits a signal
to all RF-receiver front-end components over a parallel or serial bus, and
requires the front-end components to listen for their address over the parallel
or serial bus.” App. Br. 20; Reply Br. 10. But that contention disregards
Roller’s disclosure concerning a register in the controller device providing
control signals for front-end components. In particular, Roller explains that
a register in the controller device provides an appropriate “configuration
pattern comprising a plurality of bits in parallel” to “control pins” for the
front-end sub-circuits. Roller || 36, 46, 50-51, Figs. 2—3. The different
configuration patterns identify various subsets of the “control pins” through
different logic-high/logic-low combinations corresponding to control signals
for selected front-end sub-circuits. Id. Tflf 5—9, 36, 46, 50-51, Figs. 2—3.
Appellants assert that “the pre-stored bit patterns in Devison control
multiple peripheral components, and thus are not the same as one or more
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I/O pins that are mapped to one RF front-end component based on an
address for the RF front-end component indicated by the command.” App.
Br. 22. But that assertion overlooks Devison’s disclosure regarding a bit
pattern “provided in parallel to statically control individual control lines,”
e.g., to enable “exactly one” amplifier “by driving its enable pin E to the
active logic level” and disabling the other amplifiers. Devison || 29, 32, 38.
Further, claims 1 and 8 require “one or more I/O pins that are . . .
mapped to an RF front-end component.” App. Br. 29, 31 (Claims App.).
The “indefinite article ‘a’ or ‘an’ in patent parlance carries the meaning of
‘one or more’ in open-ended claims containing the transitional phrase
‘comprising.’” KCJCorp. v. Kinetic Concepts, Inc., 223 F.3d 1351, 1356
(Fed. Cir. 2000). Thus, the phrase “mapped to an RF front-end component”
encompasses mapping to one or more components. Accordingly,
Appellants’ assertion that “the pre-stored bit patterns in Devison control
multiple peripheral components” does not distinguish claims 1 and 8 from
Devison. See App. Br. 22.
Appellants contend that “each front-end component has a subset of
I/O pins that are exclusive to the device” and mapped according to the
disputed “identifying” limitation. Reply Br. 10. For the reasons discussed
above, however, that contention does not comport with claim scope.
Alleged Change in Principle of Operation
Appellants argue that the Examiner erred in rejecting claims 1 and 8
because the Examiner’s combination would change the principle of
operation in Roller, Devison, and Bhanji. App. Br. 25—27. More
specifically, Appellants assert that the “Examiner has failed to establish [a]
prima facie case of obviousness because [the] Examiner has attributed
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principles of operation to the Koller, Devison, and Bhanji cited art that are
nowhere disclosed in any of Koller, Devison, and Bhanji.” Id. at 25.
We disagree. For the reasons discussed above, the Koller-Devison
combination teaches or suggests the disputed “identifying” and “sending”
limitations. See Final Act. 2-4; Ans. 2—4, 7—9.
Further, we agree with the Examiner that “[i]n analogous art, Koller,
Devison and Bhanji teach front-end control in a wireless transceiver,
wherein Devison specifically teach[es] different embodiments in
implementing flexible and scalable control interface.” Ans. 9. Koller and
Devison each describe techniques for a baseband device to control front-end
components, such as low-noise amplifiers and power amplifiers, using
pre-stored bit patterns read from a memory and provided to interface pins
mapped to front-end components. See, e.g., Koller H 5—9, 31—32, 35—36,
39-40, 45—48, 50-51, 70, Figs. 2-3; Devison H 29-38, 46-51, Fig. 3,
Fig. 6. The pre-stored bit patterns correspond to control signals for front-
end components. Bhanji similarly discloses a wireless transceiver with a
digital signal processor for, among other things, “performing baseband
modem filtering” and a field-programmable gate array with “programmable
input/output (I/O) pins” for controlling front-end components. See Bhanji
1110,19-20, Fig. 2.
Appellants have not explained how adapting Devison’s teachings or
Bhanji’s teachings to Koller would change Koller’s principle of operation.
App. Br. 25—27. Thus, Appellants have not established Examiner error.
Summary for Independent Claims 1 and 8
For the reasons discussed above, Appellants’ arguments have not
persuaded us that the Examiner erred in rejecting claims 1 and 8 for
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obviousness based on Koller, Devison, and Bhanji. Hence, we sustain the
§ 103(a) rejection of claims 1 and 8.
Dependent Claims 2-7 and 9-14
Claims 2—7 depend directly or indirectly from claim 1, while
claims 9—14 depend directly or indirectly from claim 8. App. Br. 29—32
(Claims App.). Appellants do not argue patentability separately for
dependent claims 2—7 and 9-14. App. Br. 14—27; Reply Br. 7—14. Because
Appellants do not argue the claims separately, we sustain the § 103(a)
rejection of these dependent claims for the same reasons as the related
independent claim. See 37 C.F.R. § 41.37(c)(l)(iv).
DECISION
We affirm the Examiner’s decision rejecting claims 1—14.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv). See
37 C.F.R. § 41.50(f).
AFFIRMED
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