Ex Parte Lin et al

Patent Trial and Appeal Board

Sep 7, 2018

13424484 (P.T.A.B. Sep. 7, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/424,484 03/20/2012
112165 7590 09/11/2018
STATS ChipPAC/PATENT LAW GROUP:
Atkins and Associates, P.C.
55 N. Arizona Place, Suite 104
Chandler, AZ 85225
FIRST NAMED INVENTOR
YaojianLin
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
2515.0141 DIV 2129
EXAMINER
GRAYBILL, DAVIDE
ART UNIT PAPER NUMBER
2894
NOTIFICATION DATE DELIVERY MODE
09/11/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
main@plgaz.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte YAOJIAN LIN, JIANMIN FANG,
KANG CHEN, and HAIJING CAO
Appeal2017-010533
Application 13/424,484
Technology Center 2800
Before CATHERINE Q. TIMM, N. WHITNEY WILSON, and
MICHAEL G. McMANUS, Administrative Patent Judges.
TIMM, Administrative Patent Judge.
DECISION ON APPEAL 1
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellants2 appeal from the
Examiner's decision to reject claims 1-8, 10, 11, 13-15, 17-21, 23, 24, and
26-32. We have jurisdiction under 35 U.S.C. § 6(b ).
1 In explaining our Decision, we cite to the Final Office Action of October 6,
2016 (Final), Appeal Brief of March 6, 2017 (Appeal Br.), and Examiner's
Answer of June 9, 2017 (Ans.).
2 Appellants identify the real party in interest as ST ATS ChipP AC Pte. Ltd.
Appeal Br. 1.
Appeal2017-010533
Application 13/424,484
We REVERSE.
The claims are directed to a semiconductor device. Claims 1, 7, 14,
and 21 are independent and of varying scope. Claim 14 is illustrative of one
of the broadest variations:
14. A semiconductor device, comprising:
a substrate including a semiconductor material;
a first semiconductor die disposed over a first surface of
the substrate;
a first integrated passive device (IPD) disposed over the
first surface of the substrate and laterally offset from the first
semiconductor die;
an encapsulant deposited over the first IPD; and
a second IPD formed over a surface of the encapsulant
opposite the first IPD and laterally offset from the first
semiconductor die, wherein the second IPD includes a first
conductive layer formed over the surface of the encapsulant
opposite the first IPD and wound to form an inductor.
Appeal Br. 29 ( claims appendix).
The Examiner maintains the following rejections:
A. The rejection of claims 1-6, 29, and 303 under 35 U.S.C.
§ I03(a) as obvious over Funaya4 in combination with
3 The Examiner objected to claim 30 as being a substantial duplicate of
claim 4. Final 2. Appellants state that they will cancel claim 30 pending the
outcome of the appeal. Appeal Br. 7. Thus, claim 30 should be cancelled on
return of the application to the jurisdiction of the Examiner.
4 Funaya et al., WO 2006126090 Al, pub. Nov. 8, 2007.
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Application 13/424,484
Kurita5 or Sawada, 6 and further in combination with
Hayashi; 7
B. Therejectionofclaims7,8, 10, 11, 13-15, 17, 18,20,21,
23, 24, 27, 31, and 32 under 35 U.S.C. § I03(a) as obvious
over Funaya in combination with Kurita or Sawada, and
Pohl· 8 and
'
C. The rejection of claims 19, 26, and 28 under 35 U.S.C.
§ I03(a) as obvious over Funaya, Kurita or Sawada, and
Pohl, and further in combination with Hayashi.
OPINION
First, we respond to the Examiner's observation that "the appeal brief
filed on March 06, 2017, does not comply with MPEP 1205.02 because each
ground of rejection is not argued under a separate heading which clearly
identifies the ground of rejection being contested." Ans. 23. Although
correct, this observation does not prevent us from deciding the issues
presented this appeal. We note that no Notice of Non-compliance was
issued before the Appeal Brief was forwarded to the Examiner. See MPEP
§ 1205.03 (9th ed., rev. Nov. 2015)(setting forth the procedure for issuing a
Notice of Non-compliance that was in force at the time the Appeal Brief was
filed). Once the appeal reaches the jurisdiction of the Board, it is acceptable
for the Board to review the issues if they can be reasonably determined by
5 Kurita, US 2008/0265390 Al, pub. Oct. 30, 2008.
6 Sawada, US 2003/0222350 Al, pub. Dec. 4, 2003.
7 Hayashi, US 2001/0028545 Al, pub. Oct. 11, 2001.
8 Pohl et al., US 2009/0008793 Al, pub. Jan. 8, 2009.
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Application 13/424,484
reading the Appeal Brief. We determine we are able to reach the issues in
the present case.
Rejection A
Turning first to the Examiner's rejection of claims 1---6, 29, and 30
under 35 U.S.C. § 103(a) as obvious over Funaya in combination with
Kurita or Sawada, and further in combination with Hayashi, we determine
that the Examiner inadequately supported the finding that Funaya teaches
the third conductive layer having the structure required by these claims.
Claim 1, and the other rejected claims by virtue of their dependence
from claim 1, require "a third conductive layer formed over a surface of the
encapsulant opposite the capacitor, wherein the third conductive layer is in
physical contact with the vertical interconnect structure and a portion of the
third conductive layer is wound to form an inductor." Claim 1 ( emphasis
added).
In the Final Office Action, the Examiner finds that Funaya teaches "a
third conductive layer (illustrated in 322 in figure 36, not labeled)," but does
not otherwise point out what layer is being relied on or where Funaya
describes a portion wound to form an inductor. Final 14--15. In the
rejection reproduced in the Answer, the Examiner points to layer 3a of
Funaya, but again does not point out where Funaya teaches the required
wound portion that forms an inductor. Ans. 15. Nor does the Examiner
address Appellants' argument (Appeal Br. 9-10) on the matter. Ans. 26-27.
Funaya discloses layer 3a is conductive wiring and describes forming
this conductive wiring 3a on the surface of insulating resin layer 11. Funaya
,r,r 72, 164, 184, Figs. 14, 18. However, Funaya lacks a clear disclosure of a
wound portion forming an inductor. Under the circumstances, it was
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Application 13/424,484
incumbent on the Examiner to point to the specific disclosure the Examiner
was relying on to support the finding.
Appellants have identified a reversible error in the Examiner's
rejection of claims 1---6, 29, and 30 under 35 U.S.C. § 103(a) as obvious over
Funaya in combination with Kurita or Sawada, and further in combination
with Hayashi.
Rejections B and C
TheExaminerrejectsclaims7,8, 10, 11, 13-15, 17, 18,20,21,23,
24, 27, 31, and 32 under 35 U.S.C. § 103(a) as obvious over Funaya in
combination with Kurita or Sawada, and Pohl and further relies on Hayashi
to reject claims 19, 26, and 28.
All of the rejected claims, by virtue of their dependency from claims
7, 14, and 21, are directed to a semiconductor device including either a
semiconductor substrate ( claim 7) or a substrate including a semiconductor
material ( claims 14, 21 ). On the substrate are a first semiconductor die and
first integrated passive device (IPD) laterally offset from the die ( claims 7,
14, 21 ). A conductive layer wound to form an inductor resides on the
surface of an encapsulant ( claims 7, 14, 21 ).
The Examiner again cites to Figure 36 of Funaya, a figure without any
of the reference numerals cited by the Examiner, to find that Funaya teaches
a substrate 10, a semiconductor die 1, an IPD 12, an encapsulant 8, 11, and a
conductive layer. Final 3--4. In the Answer, the Examiner points also to
Figure 18. Ans. 2. The Examiner acknowledges that Funaya "does not
appear to explicitly disclose" a semiconductor substrate ( claim 7) or a
substrate including a semiconductor material ( claims 14, 21 ). Final 7.
However, the Examiner determines it would have been obvious to have
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Application 13/424,484
substituted the substrate of Kurita or Sawada for Funaya's substrate. Final
7-11. The Examiner also acknowledges that "the combination of applied
prior art does not appear to explicitly disclose" the conductive layer formed
over the encapsulant surface and wound to form an inductor. Final 11.
However, the Examiner determines it would have been obvious to have so
formed such a conductive layer based on the teachings of Pohl. Final 11-12.
We agree with Appellants that the evidence does not support the
Examiner's finding of a reason to make the substitutions such that the
semiconductor device of claims 7, 14, and 21 results.
Funaya is directed to a circuit board having functional elements built
into it. Funaya ,r 1. In Figure 1, this circuit board is depicted with
functional element 1 as embedded in a circuit board having a base layer 8
and conductive wiring 3 and 4. Funaya ,r 73. Funaya discloses forming the
base layer 8 of insulating material such as glass or aramid reinforced epoxy
resin. Funaya ,r 7 5.
In Figure 2, Funaya depicts a circuit board with a base material of at
least three insulating resin layers that suppresses the formation of cracks
produced due to stresses generated by the differences in thermal coefficients
of expansion between the functional element 1 and the insulating layer 8.
Funaya ,r 82. This embodiment includes insulating layer 10, which the
Examiner finds is a substrate. Funaya ,r 83; Final 3. Funaya teaches
forming insulating layer 10 of insulating material such as epoxy or
polyimide. Funaya ,r 85.
Kurita and Sawada are directed to semiconductor devices, not printed
circuit board devices. Kurita ,r 3; Sawada ,r 3. In essence, these references
teach placing semiconductor chips on a silicon interposer such that one can
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Application 13/424,484
connect the communication paths through the interposer. Kurita ,r 21;
Sawada ,r 28. Ultimately such semiconductor devices containing interposers
would be further mounted onto a circuit board. The interposer is not a
substitute for a printed circuit board. Thus, these reference do not support
the Examiner's finding of a suggestion to use the material of Kurita's or
Sawada's interposers as a substitute for the material of Funaya's insulating
layer 10, which is part of a printed circuit board.
The Examiner's reasoning as to Pohl is also lacking. Pohl, like Kurita
and Sawada, is directed to a semiconductor device. Pohl ,r 1. Pohl embeds a
semiconductor chip 101 in a molding compound layer 102. Pohl ,r 24, Fig.
1. Pohl then arranges a third electrically conductive layer 111 above the
surface 104 of molding compound layer 102. Pohl ,r 26, Fig. 3. The third
electrically conductive layer 111 may form inductor coils. Pohl ,r 23.
Referring to claim 7, the Examiner finds that Pohl discloses forming
IPD 111 over a surface of encapsulant 109 opposite the first IPD and
laterally offset from first semiconductor die 101, wherein the second IPD
includes first conductive layer 111 formed over the surface of the
encapsulant and wound to form an inductor (inductor coils). Final 11. The
Examiner, however, does not explain how this combination results in both a
first semiconductor die and a first IPD formed over the first surface of the
semiconductor substrate in the required laterally offset location in addition
including the second IPD (inductor coil). Funaya and Pohl each disclose a
single functional element ( element 1 in Funaya, Fig. 1; element 101 in Pohl,
Fig. 3). The Examiner does not provide a convincing suggestion to include
both a first semiconductor die and a first IPD in the location required by
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claim 7. The error is repeated by the Examiner in rejecting claims 14 and
21. Final 11-12.
Appellants have identified a reversible error in the Examiner's
rejection of claims 7, 8, 10, 11, 13-15, 17, 18, 20, 21, 23, 24, 27, 31, and 32
under 35 U.S.C. § 103(a) as obvious over Funaya in combination with
Kurita or Sawada, and Pohl. The defects are not cured by the Examiner's
reliance on Hayashi to reject claims 19, 26, and 28.
CONCLUSION
In summary, we do not sustain any of the Examiner's rejections.
DECISION
The Examiner's decision is reversed.
REVERSED
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