Ex Parte Lin et al

Patent Trial and Appeal Board

Aug 29, 2018

13832205 (P.T.A.B. Aug. 29, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/832,205 03/15/2013
112165 7590 09/07/2018
STATS ChipPAC/PATENT LAW GROUP:
Atkins and Associates, P.C.
55 N. Arizona Place, Suite 104
Chandler, AZ 85225
FIRST NAMED INVENTOR
YaojianLin
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
2515.0408 6197
EXAMINER
NGUYEN, DILINH P
ART UNIT PAPER NUMBER
2894
NOTIFICATION DATE DELIVERY MODE
09/07/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
main@plgaz.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte Y AOJIAN LIN and KANG CHEN
Appeal2018-001221
Application 13/832,205
Technology Center 2800
Before LINDA M. GAUDETTE, JEFFREY B. ROBERTSON, and
BRIAND. RANGE, Administrative Patent Judges.
ROBERTSON, Administrative Patent Judge.
DECISION ON APPEAL
Appeal 2018-001221
Application 13/832,205
STATEMENT OF CASE
Appellant1 appeals under 35 U.S.C. § 134 from the Examiner's
rejections of claims 14--21 and 24--38. We have jurisdiction under 35 U.S.C.
§ 6(b ).
We REVERSE.
THE INVENTION
Appellant states that the invention relates in general to semiconductor
devices and methods of forming dual-sided interconnect structures. (Spec.
Figure 4b is an embodiment showing a portion of a process for
forming an interposer substrate 155 with a semiconductor die mounted
thereon and is reproduced below:
F'iO. 4b
Figure 4b depicts, inter alia, an electrically conductive bump material
156 deposited over a conductive layer 150. (Spec. ,r,r 15, 44.)
1 The Appellant is the applicant, ST ATS ChipP AC Pte. Ltd., formerly
STATS ChipPAC, Ltd., which according to the Appeal Brief, is also the real
party in interest. (Appeal Brief filed May 22, 2017, hereinafter "App. Br.,"
1.)
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Application 13/832,205
Figure 9 is an embodiment of an interposer substrate with an exposed
side surface of a bump and is reproduced below:
;::,14'0
' i
············.:r······s···
: ·4 t7B
Figure 9 illustrates an embodiment of the wafer level chip scale
package (WLCSP) depicting a portion of cores substrate 140 being removed
by laser 244 to expose a surface of bump 156 for electrical interconnect to
external semiconductor devices. (Spec. ,r,r 15, 65.)
Claims 14 and 20, reproduced below, are illustrative of the claimed
subject matter ( emphases added):
14. A semiconductor device, comprising:
a substrate;
a vertical interconnect structure formed in contact with a
first surface of the substrate, wherein the substrate includes an
opening extending from a second surface of the substrate
opposite the first surface of the substrate to the vertical
interconnect structure;
a semiconductor die disposed over the first surface of the
substrate;
an encapsulant deposited over the first surface of the
substrate, a side surface of the substrate, and around the
semiconductor die, including a surface of the encapsulant
outside the substrate coplanar with the second surface of the
substrate; and
a first interconnect structure formed over the encapsulant
opposite the substrate and coupled to the semiconductor die.
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Appeal 2018-001221
Application 13/832,205
20. A semiconductor device, comprising:
a substrate including,
(a) a core material,
(b) a first conductive layer formed over a first
surface of the core material,
( c) a second conductive layer formed over a
second surface of the core material opposite the first
surface, and
( d) a conductive via formed through the core
material and contacting the first conductive layer and
second conductive layer;
a bump formed over the first conductive layer;
a semiconductor die disposed over a first surface of the
substrate and first conductive layer;
an encapsulant deposited over the substrate and around
the semiconductor die including a surface of the encapsulant
outside the substrate coplanar with a second surface of the
substrate opposite the first surface of the substrate; and
a first interconnect structure formed over the encapsulant
opposite the substrate and coupled to the semiconductor die.
(App. Br., Claims Appendix 9, 11.)
THE REJECTIONS
The Examiner rejected claims 14--16, 18, 20, 21, 24, 26-30, and 32-
3 8 under pre-AIA 35 U.S.C. § 102(b) as anticipated by Chi et al. (US
2011/0068444 Al, published March 24, 2011, hereinafter "Chi").
The Examiner rejected claims 19, 25, and 31 under pre-AIA 35 U.S.C.
§ I03(a) as obvious over Chi.
The Examiner rejected claim 17 under pre-AIA 35 U.S.C. § I03(a) as
obvious over Chi in view of Boon et al. (US 7,855,462 B2, issued December
21, 2010) (hereinafter "Boon").
(Final Office Action, mailed December 20, 2016, hereinafter "Final Act.,"
2---6; Examiner's Answer, mailed October 2, 2017, hereinafter "Ans.," 2.)
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Application 13/832,205
ISSUES
The Examiner found, inter alia, that Chi discloses a semiconductor
device as recited in claim 14, and in particular that "substrate 149 includes
an opening extending from a second surface of the substrate 149 opposite
the first surface of the substrate 149 to the vertical interconnect structure 212
(fig 10)." (Final Act. 2.) To further illustrate the Examiner's position, the
Examiner provided an annotated version of Chi's Figure 10, reproduced
below from the Examiner's Answer (page 4):
The annotated version of Figure 10 depicts a wafer level chip scale
module package (WLCSMP) with conductive pillars 212 through
encapsulant 140, interposer 149, through silicon vias (TSVs) 122, and
interconnect structure 214 formed over semiconductor die 132. (Chi ,r,r 8,
22, 63.) The Examiner's annotations indicate first and second surfaces of
interposer 149 and "an opening" at each of TSVs 122. In the Answer, the
Examiner stated that interposer 149 and conductive pillars 212 correspond to
the claimed "substrate" and "vertical interconnect structure," respectively,
and each of TSV s 122, as identified in annotated Figure 10, corresponds to
the claimed "opening." (Ans. 2-3.)
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Appeal 2018-001221
Application 13/832,205
Appellant argues that contrary to the Examiner's position, interposer
149 as disclosed in Chi does not have an opening extending from a second
surface opposite the first surface to conductive pillars 212 but that interposer
149 is solid in this area. (App. Br. 6.)
Regarding claim 20, the Examiner found, inter alia, that Chi discloses
a "bump" disposed over the first conductive layer as recited in the claim
relying on each of conductive pillars 212 disclosed in Chi as corresponding
to the bump. (Final Act. 3.) The Examiner relied on a dictionary definition
of "bump" as being "a raised area on a surface," in concluding the claim
term "bump" would encompass the conductive pillars disclosed in Chi.
(Ans. 5 (citing CambridgeDictionary
http://dictionary.cambridge.org/us/ dictionary/ english/bump ). )
Appellant contends that conductive pillars 212 disclosed in Chi are
not "bumps" as recited in claim 20. (App. Br. 7.)
Therefore, the dispositive issues on appeal are:
Did the Examiner err in finding that the "opening" recited in claim
14 reads on Chi's TSVs?
Did the Examiner err in finding that the "bump" recited in claim 20
read on Chi's conductive pillars?
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Appeal 2018-001221
Application 13/832,205
DISCUSSION
Claim 14
We are persuaded by Appellant's argument that the Examiner erred in
finding that Chi discloses that TSV 122 corresponds to an opening extending
from a second surface of the substrate opposite the first surface of the
substrate to the vertical interconnect structure. In particular, Chi discloses
that the through silicon vias are formed using a laser drilling or etching
process and then the vias are filled with electrically conductive material.
(Chi ,r 42.) Thus, as Appellant points out, a filled via is not an opening as it
contains conductive material. (Reply Brief filed November 15, 2017, 2-3.)
The Examiner has not sufficiently explained why Chi discloses an opening.
Accordingly, we reverse the Examiner's rejection of independent
claim 14 and the claims dependent therefrom.
Claim 20
We are persuaded by Appellant's argument that one of ordinary skill
in the art would not have understood the conductive pillars disclosed in Chi
to be a "bump" as recited in claim 20. (App. Br. 7 ( citing Spec. ,r 44, Fig. 4b
(reproduced above)).) In addition, the Specification discloses that bump
materials are deposited "using evaporation, electrolytic plating, electroless
plating, ball drop, or screen printing process." (Spec. ,r 54.) Thus, the
Specification itself is evidence of the difference between a "bump" and a
"conductive pillar."
We observe that Chi, in discussing "bumps," discloses: "Bumps 156
represent one type of interconnect structure that can be formed over
conductive layer 154. The interconnect structure can also use stud bumps,
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Appeal 2018-001221
Application 13/832,205
micro bumps, conductive pillars, conductive paste, or other electrical
interconnect." (i-f 54.) Moreover, Chi discloses that conductive pillars are
formed by laser drilling or etching vias and filling the vias with conductive
material. (i-f 64.) Thus, Chi discusses bumps and conductive pillars as being
different structures.
We also observe that the definition relied on by the Examiner is from
a general purpose dictionary ( citing a mosquito bite as an example of a
bump), and in view of the intrinsic evidence of record in the form of the
prior art cited and the Specification, we are of the view that intrinsic
evidence is more consistent with how one of ordinary skill in the art would
have interpreted the terms "bump" and "conductive pillar."
Accordingly, we reverse the Examiner's decision to reject claim 20
and the claims dependent therefrom. In addition, because independent claim
26 contains the "bump" limitation discussed above, we reverse the
Examiner's rejection of claim 26 and the claims dependent therefrom.
Obviousness Rejections
The obviousness rejections of dependent claims 17, 19, 25, and 31 are
based on the same erroneous findings with respect to the teachings of Chi
discussed above. As a result, we reverse the rejections of claims 17, 19, 25,
and 31 for the same reasons discussed above for independent claims 14, 20,
and 26.
CONCLUSION
The Examiner erred in finding that the "opening" recited in claim 14
reads on the TSV s disclosed in Chi.
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Application 13/832,205
The Examiner erred in finding that the "bump" recited in claim 20
reads on the conductive pillars disclosed in Chi.
DECISION
We reverse the Examiner's rejection of claims 14--21 and 24--38.
REVERSED
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