Ex Parte Lin

Patent Trial and Appeal Board

Sep 9, 2016

11949282 (P.T.A.B. Sep. 9, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
111949,282 12/03/2007
112165 7590 09/13/2016
STATS ChipPAC/PATENTLAWGROUP:
Atkins and Associates, P.C.
55 N. Arizona Place, Suite 104
Chandler, AZ 85225
FIRST NAMED INVENTOR
YaojianLin
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
2515.0078 4480
EXAMINER
DANG, TR UNG Q
ART UNIT PAPER NUMBER
2819
NOTIFICATION DATE DELIVERY MODE
09/13/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
main@plgaz.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte Y AOJIAN LIN
Appeal2015-004124
Application 11/949,282
Technology Center 2800
Before MAHSHID D. SAADAT, JOHNNY A. KUMAR, and
JON M. JURGOV AN, Administrative Patent Judges.
KUMAR, Administrative Patent Judge.
DECISION ON APPEAL
Appellant1 appeals under 35 U.S.C. § 134(a) from the Final Rejection
of claims 1, 2, 4, 8-11, 14, 34--42, and 47---63.2 We have jurisdiction under
35 U.S.C. § 6(b).
We affirm.
1 According to Appellant, the real party in interest is ST ATS ChipP AC, Ltd.
(Br. 1 ).
2 Claims 3, 5-7, 12, 13, 15-33, and 43--46 have been canceled.
Appeal2015-004124
Application 11/949,282
STATEMENT OF THE CASE
Invention
Appellant's invention relates to forming a wafer level interconnect
structure on a dummy substrate prior to mounting a semiconductor die,
which allows higher processing temperatures to be used to form the
interconnect structure (Spec. i-f 41 ).
Representative Claim
1. A method of making a wafer level chip scale package,
compnsmg:
providing a temporary wafer level substrate;
forming a wafer level interconnect structure over the
temporary wafer level substrate using wafer level processes
including forming a first passivation layer continuously over
and in direct contact with a surface of the temporary wafer level
substrate, and forming a first conductive layer in direct contact
with a surface of the first passivation layer as formed
continuously over the surface of the temporary wafer level
substrate;
disposing a first semiconductor die over the wafer level
interconnect structure such that an active surface of the first
semiconductor die is in electrical contact with the first
conductive layer;
depositing a first encapsulant over the wafer level
interconnect structure and the first semiconductor die;
depositing a second encapsulant over a surface of the first
encapsulant opposite the wafer level interconnect structure, the
first and second encapsulants being cured simultaneously;
removing the temporary wafer level substrate to expose
the first passivation layer;
removing a first portion of the first passivation layer to
expose the first conductive layer after removing the temporary
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Application 11/949,282
wafer level substrate while retaining a second portion of the
first passivation layer in the wafer level interconnect structure;
forming a first under bump metallization (UBM) in
electrical contact with the first conductive layer after removing
the first portion of the first passivation layer; and
forming a plurality of bumps on the first UBM.
The Examiner's Rejections
Claims 1, 2, 4, 34--36, and 38 are rejected under 35 U.S.C. § 103(a) as
being unpatentable over Ogawa et al. (US 2004/0056344 Al; published Mar.
25, 2004), Kimbara et al. (US 5,321,210; issued June 14, 1994), Coyle (US
6,518,089 B2; issued Feb. 11, 2003), and Li et al. (US 6,312,830 Bl; issued
Nov. 6, 2001) (Ans. 8-12).
Claims 8, 14, 39, 40, 42, 47--49, 52, 54, 56, 57, 59, and 62 are rejected
under 35 U.S.C. § 103(a) as being unpatentable over Ogawa and Kimbara
(ii .. ns. 2-6).
Claims 9, 11, 53, and 60 are rejected under 35 U.S.C. § 103(a) as
being unpatentable over Ogawa, Kimbara, and Li (Ans. 8).
Claim 10 is rejected under 35 U.S.C. § 103(a) as being unpatentable
over Ogawa, Kimbara, and Chen et al. (US 7,125,745 B2; issued Oct. 24,
2006) (Ans. 13).
Claim 37 is rejected under 35 U.S.C. § 103(a) as being unpatentable
over Ogawa, Kimbara, Coyle, Li, and Matsui et al. (US 6,662,442B1; issued
Dec. 16, 2003) (Ans. 12).
Claims 41, 51, and 61 are rejected under 35 U.S.C. § 103(a) as being
unpatentable over Ogawa, Kimbara, and Matsui (Ans. 7-8).
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Application 11/949,282
Claims 50 and 58 are rejected under 35 U.S.C. § 103(a) as being
unpatentable over Ogawa, Kimbara, and Coyle (Ans. 6-7).
Claims 55 and 63 are rejected under 35 U.S.C. § 103(a) as being
unpatentable over Ogawa, Kimbara, and Fuller et al. (US 2005/0287706 Al;
published Dec. 29, 2005) (Ans. 13-14).
Appellant's Contentions
Regarding independent claim 1, Appellant contends the following:
(1) Ogawa does not teach the claimed "first passivation layer,"
because Ogawa's thin film layer (23) is completely removed from the
surface of the multi-layer wiring section, whereas claim 1 requires retaining
a portion of the first passivation layer (Br. 10-13).
(2) The combination of Kimbara with Ogawa is improper, because it
would change the principle of operation of Ogawa (Br. 15-17). Ogawa
teaches the surface of the wiring layer (8) is highly planarized, and forming
via holes in Ogawa's thin film (23), as taught by Kimbara, would not leave
the wiring layer with a planarized surface (id.). Further, forming the
polyimide layers (102, 104) ofKimbara over the substrate of Ogawa would
require forming Ogawa's thin resin film (23) and thin metal film (22) of the
same polyimide material (id.).
(3) Coyle does not teach "depositing a first encapsulant over the wafer
level interconnect structure and the first semiconductor die," because
Coyle's first encapsulant (54) is an underfill material that is dispensed under
each chip ( 50), and one of ordinary skill in the art would not view the
underfill material as being deposited over both the chip and the substrate
(Br. 18).
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Application 11/949,282
( 4) Li does not teach removing a temporary wafer level substrate or a
portion of the first passivation layer prior to forming the under bump
metallization (Br. 21-22).
(5) Ogawa, Kimbara, and Li are silent regarding a second encapsulant
being deposited over a surface of the first encapsulant (Br. 12, 14, and 21).
( 6) Ogawa, Kimbara, and Coyle are silent regarding an under bump
metallization being formed in electrical contact with the first conductive
layer (Br. 13, 15, and 20).
(7) Coyle is silent regarding a wafer level interconnect structure
including a first passivation layer formed over a temporary substrate (Br.
18-20).3
ANALYSIS
We have reviewed the Examiner's rejections in light of Appellant's
arguments (Br. 7----22) that the Examiner erred in rejecting claim 1. We
disagree with Appellant's above contentions (1}-(7). We adopt as our own
1) the findings and reasons set forth by the Examiner in the Final Office
Action from which this appeal is taken (Final Act. 2-14) and 2) the reasons
set forth by the Examiner in the Examiner's Answer (Ans. 14----24) in
response to Appellant's Appeal Brief. We concur with the conclusions
reached by the Examiner. We highlight and address specific findings and
arguments for emphasis as follows.
3 Independent claims 8, 4 7, and 5 6 are argued on a similar basis as
independent claim 1 (Br. 22-35), and separate patentability is not argued for
the dependent claims (id.). Except for our ultimate decision, these claims
are not discussed further.
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Application 11/949,282
Issue 1: Under§ 103(a), did the Examiner err by finding the
combination of Ogawa and Kimbara teaches the claimed "first passivation
layer"?
Appellant's contention (1) that Ogawa's thin film layer is completely
removed and, thus, cannot teach the claimed "first passivation layer" is not
persuasive of Examiner error in the rejection of claim 1. The Examiner
properly relies on In re Keller, 642 F .2d 413, 425 (CCP A 1981 ), and states
that nonobviousness cannot be established by attacking the Ogawa reference
individually when the rejection is predicated upon a combination of Ogawa
and Kimbara (Ans. 17-19). We agree with the Examiner's finding that
Kimbara teaches the concept of removing only a first portion of a
passivation layer to form via openings to a metallization layer, while
retaining a second portion of the passivation layer over an interconnect
structure (Ans. 18 (citing Kimbara, Figs. 22(D}-22(E): vias 105 formed in
passivation layer 104)). Furthermore, the Examiner has provided "some
articulated reasoning with some rational underpinning to support the legal
conclusion of obviousness" for combining this teaching of Kimbara with
Ogawa' s method of forming a wafer level interconnect structure, specifically
that retaining a portion of the passivation layer would protect the
interconnect structure from contamination (Ans. 19; see KSR Int'! Co. v.
Teleflex, Inc., 550 U.S. 398, 417-18 (2007) (quoting In re Kahn, 441 F.3d
977, 988 (Fed. Cir. 2006))).
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Issue 2: Under§ 103(a), is the combination of Ogawa and Kimbara
improper because it changes the principle of operation of Ogawa?
We are not persuaded of error by Appellant's contention (2) that
modifying Ogawa with Kimbara would change the principle of operation of
Ogawa. The Examiner's proffered combination of Ogawa and Kimbara
does not require replacing the thin metal film (22) of Ogawa, rather, it
requires retaining Ogawa's thin resin film (23) on the multi-layer wiring
after removing the temporary substrate and forming via openings in the resin
film, as taught by Kimbara (Ans. 18-19). Further, Ogawa does not require a
planarized surface above the multi-level wiring (8), as shown in Figure 21,
where the solder bumps ( 44) render the surface non-planar. Thus, we are
unpersuaded that leaving a portion of the first passivation film over Ogawa's
multi-layer wiring (8) and under the solder bumps (44) would change the
principle of operation of Ogawa.
Issue 3: Under§ 103(a), did the Examiner err by finding Coyle
teaches "depositing a first encapsulant over the wafer level interconnect
structure and the first semiconductor die"?
Appellant's contention (3) regarding the underfill material of Coyle
does not persuade us of error in the rejection of claim 1. The Examiner finds
the term "over" is a relative term that depends on the orientation of the
object (Ans. 21 ). Under the broadest reasonable interpretation consistent
with Appellant's disclosure, we agree with the Examiner's finding that
Coyle's underfill encapsulant (54) is deposited "over" the bottom surface of
the semiconductor die (50) (Ans. 21; see In re Morris, 127 F.3d 1048, 1054
(Fed. Cir. 1997): claim language is given its broadest reasonable
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Application 11/949,282
interpretation during prosecution). Thus, we agree with the Examiner's
finding that Coyle teaches depositing a first encapsulant (i.e., underfill
encapsulant 54) over the bottom surface of the semiconductor die and over
the substrate, depositing a second encapsulant (i.e., encapsulant 58) over the
first encapsulant, and curing the first and second encapsulants
simultaneously (Ans. 9 (citing Coyle, Figs. 5b-5c and col. 6: 13-29, 53-57)).
Additionally, the Examiner has provided a sufficient rationale to combine
this teaching of Coyle with Ogawa and Kimbara, specifically that utilizing
an underfill process mitigates stress within the packaged semiconductor
device (Ans. 20 (citing Coyle, col. 3:25-35); see KSR, supra).
Issue 4: Under§ 103(a), did the Examiner err by finding Li teaches
forming the claimed "under bump metallization"?
We are not persuaded of Examiner error by Appellant's contention
(4), and agree with the Examiner; s finding that Li teaches forming an under
bump metallization (Ans. 20 (citing Li, col. 1: 15-30)) after removing a first
portion of a first passivation layer (see also Li, Fig. la (as cited by Appellant
(Br. 21)), opening formed in passivation layer 50). Appellant's contention
that Li does not teach removing a temporary substrate prior to forming the
under bump metallization is not persuasive of error, because nonobviousness
cannot be established by attacking the Li reference individually when the
rejection is predicated upon the combination of Ogawa, Kimbara, and Li
(see Ans. 20, 22-23; see In re Keller, supra). We find the Examiner's
rationale to combine Li with Ogawa and Kimbara, to improve adhesion of
the solder bump to the metallization layer (Ans. 20), to be sufficient to
support the conclusion of obviousness (see KSR, supra.)
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Issue 5: Under§ 103(a), did the Examiner err in the rejection of claim
1 because the cited references are silent regarding the limitations disputed in
Appellant's contentions (5}-(7)?
Appellant's contentions (5}-(7) do not persuade us of Examiner error,
because nonobviousness cannot be established by attacking each reference
individually when the rejection is predicated upon the combination of
Ogawa, Kimbara, Coyle, and Li (see Ans. 17-23; see In re Keller, supra).
As discussed with respect to Issues ( 1}---(4 ), we agree with the Examiner's
findings that the combination of references teaches the disputed limitations
of claim 1.
CONCLUSION
For the reasons set forth above, we sustain the Examiner's rejection of
independent claim 1under35 U.S.C. § 103(a) as unpatentable over Ogawa,
Kimbara, Coyle, and Li.
DECISION
We affirm the Examiner's rejections of claims 1, 2, 4, 8-11, 14, 34--
42, and 47---63 under 35 U.S.C. § 103(a).
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED
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