Ex Parte Lim et al

Patent Trial and Appeal Board

Dec 22, 2016

13873459 (P.T.A.B. Dec. 22, 2016)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/873,459 04/30/2013 Kevin T. Lim 83206029 2654
56436 7590 12/27/2016
Hewlett Packard Enterprise
3404 E. Harmony Road
Mail Stop 79
Fort Collins, CO 80528
EXAMINER
DOAN, KHOA D
ART UNIT PAPER NUMBER
2133
NOTIFICATION DATE DELIVERY MODE
12/27/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
hpe.ip.mail@hpe.com
chris. mania @ hpe. com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte KEVIN T. LIM, SAI RAHUL CHALAMALASETTI,
JICHUAN CHANG, and MITCHEL E. WRIGHT
Appeal 2016-004005
Application 13/873,459
Technology Center 2100
Before JOSEPH L. DIXON, JAMES R. HUGHES, and ERIC S. FRAHM,
Administrative Patent Judges.
FRAHM, Administrative Patent Judge.
DECISION ON APPEAL
Appeal 2016-004005
Application 13/873,459
STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134 from the Final Rejection of
claims 1—18. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.
The invention relates to caching objects in a hash table (Spec. 19).
Claim 1, reproduced below, is illustrative of the claimed subject matter:
1. An apparatus comprising:
a memory caching circuit to cache objects, the objects
being cached in at least one hash table, the at least one hash table
having a predetermined arrangement, wherein the memory
caching circuit is a field programmable gate array (FPGA); and
a network interface to establish communication between
the memory caching circuit and a network, the communication
permitting the memory caching circuit to receive an object from
a remote device for caching and to transmit a cached object to a
remote device requesting the cached object.
REFERENCES
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Chatterjee
Sundarrajan
Sadri
Levy
US 7,058,639 B1
US 2007/0156965
US 2013/0159629
US 2014/0310307
June 6, 2006
A1 July 5, 2007
A1 June 20, 2013
A1 Oct. 16,2014
REJECTION
The Examiner made the following rejection:
Claims 1—18 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Sadri, Levy, Chatterjee, and Sundarrajan.
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ANALYSIS
Appellants contend:
Chatterjee fails to provide any teaching or even a suggestion that
the network interface 918 may be used in the manner recited in
the pending claims. Chatterjee merely discloses that the
“[cjommunication interface 918 provides a two-way data
communication coupling to a network link 920 that is connected
to a local network 922.” Chatterjee provides no disclosure of any
particular use of the network link 920, let alone of “receive an
object from a remote device for caching and to transmit a cached
object to a remote device requesting the cached object,” as
recited in pending claim 1.
(App. Br. 7 (citation omitted)). Appellants also contend one of ordinary skill
in the art would not have combined the cited references because “[tjhere is
no indication in any reference that using an FPGA provides any ‘capability
to incorporate various type of hardware and improve compatibility of the
system, ’ as alleged by the Examiner,” and “none of the references attempt to
address the performance bottlenecks or the power consumption issues in
Memcached systems addressed by examples of Appellant’s disclosure”
(App. Br. 9). We are not persuaded by Appellants’ arguments.
We first note that the claim 1 language “to establish communication
between the memory caching circuit and a network, the communication
permitting the memory caching circuit to receive an object from a remote
device for caching and to transmit a cached object to a remote device
requesting the cached object” recites functional limitations of the claimed
“network interface.” While Appellants are “free to recite features of an
apparatus either structurally or functionally,” functional language that does
not limit a claimed feature to a specific structure covers all devices capable
of performing the recited function. In re Schreiber, 128 F3d 1473, 1478—79
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Application 13/873,459
(Fed. Cir. 1997) (“The Board’s finding that. . . figure 5 of Harz would be
capable of performing all the functions recited in Schreiber’s claim 1 is a
factual finding, which has not been shown to be clearly erroneous. On this
ground alone, the Board’s . . . ruling must be upheld.”). See also, In re
Translogic Tech., Inc., 504 F.3d 1249, 1258 (Fed. Cir. 2007) (“[T]he term
‘coupled to receive’ in the phrase ‘input terminals “coupled to receive” first
and second input variables’ does not specify a particular connection. In
other words, the claimed circuit does not require any specific input or
connection. . . . Therefore, this court agrees with the Board’s construction
that ‘coupled to receive’ means ‘capable of receiving.’”). Accordingly, we
find that the claimed “network interface” need only be capable of
establishing “communication between the memory caching circuit and a
network.” The functional language “the communication permitting the
memory caching circuit to receive an object from a remote device for
caching and to transmit a cached object to a remote device requesting the
cached object” does not further limit the structure of the “network interface”
because it merely describes the receipt and transmission of data. In other
words, the claimed “network interface” is a generic interface for connecting
to a network.
Chatterjee discloses “a multi-level hash table” which “may be
implemented ... in a cache” (Chatterjee, col. 4,11. 5—22). And, Chatterjee
describes hardware for implementing the multi-level hash table that includes
a computer system 900 with a communication interface 918 that “provides a
two-way data communication coupling to a network link 920 that is
connected to a local network 922” (Chatterjee, col. 11,11. 38-41).
Therefore, we find Chatterjee’s communication interface 918 meets the
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Appeal 2016-004005
Application 13/873,459
claim 1 limitation “a network interface,” as construed above, because it is
capable of connecting a cache to a network.
Additionally, in the Answer, the Examiner finds Sundarrajan teaches
the disputed functional limitations of the “network interface” by disclosing
“the appliance 104 includes cache management logic to monitor[] object
requests made by clients 102a—102n to any of servers 106a—106n. Objects
returned from servers in response to these object requests are stored in the
cache memory by appliance 104.” (Ans. 5). Appellants have not provided
specific arguments rebutting these findings; rather, Appellants merely recite
the language of claim 1 in asserting Sundarrajan fails to teach the claimed
“network interface” (Reply Br. 2—3). Accordingly, even if we were to
interpret the functional language of claim 1 as further limiting the “network
interface,” we are not persuaded that Sundarrajan fails to teach the
functional limitations.
We are also not persuaded by Appellants’ arguments that it would not
have been obvious to combine the cited references. First, we agree with the
Examiner that it would have been obvious to use an FPGA to implement the
claimed “memory caching circuit” in the Examiner’s combination (Ans. 8).
Specifically, “Sundarrajan teaches that several techniques, including Field
Programmable Gate Array (FPGA), can be used to implement the cache
manager, [and] one of ordinary skill in the art would have had a reasonable
expectation of success at using an FPGA to implement the cache” (id.).
Indeed, where a claim recites “a structure already known in the prior art that
is altered by the mere substitution of one element for another known in the
field, the combination must do more than yield a predictable result.” KSR
Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007). Here, it would have
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Application 13/873,459
been obvious to use an FPGA to implement the hash table cache in the
combination of Sadri, Levy, and Chatterjee because this was a known
integrated circuit type for providing caching functions as evidenced by
Sundarrajan.
Second, Appellants’ argument that “none of the references attempt to
address the performance bottlenecks or the power consumption issues”
addressed by Appellants’ Specification (App. Br. 9) is not persuasive
because the obviousness analysis is not limited “only to the problem the
[applicant] was trying to solve.” KSR, 550 U.S. at 420. “Under the correct
analysis, any need or problem known in the field of endeavor at the time of
invention and addressed by the [application] can provide a reason for
combining the elements in the manner claimed.” Id.
We are, therefore, not persuaded the Examiner erred in rejecting claim
1, and claims 2—18 not specifically argued separately.
CONCLUSION
The Examiner did not err in rejecting claims 1—18 under 35 U.S.C.
§ 103(a).
DECISION
For the above reasons, the Examiner’s rejection of claims 1—18 is
affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
AFFIRMED
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