Ex Parte Lien et al

Board of Patent Appeals and Interferences

Mar 22, 2011

11281832 (B.P.A.I. Mar. 22, 2011)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte WEI-HAN LIEN, DANIEL C. MURRAY, and
JUNJI SUGISAWA
____________

Appeal 2009-009226
Application 11/281,832
Technology Center 2100
____________

Before HOWARD B. BLANKENSHIP, JOHN A. JEFFERY, and
ST. JOHN COURTENAY III, Administrative Patent Judges.

BLANKENSHIP, Administrative Patent Judge.

DECISION ON APPEAL1

1 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, or for filing a request for rehearing,
as recited in 37 C.F.R. § 41.52, begins to run from the “MAIL DATE”
(paper delivery mode) or the “NOTIFICATION DATE” (electronic delivery
mode) shown on the PTOL-90A cover letter attached to this decision.

Appeal 2009-009226
Application 11/281,832

2
STATEMENT OF THE CASE
This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s final
rejection of claims 1, 4-10, 12-18, 21, and 23-26, which are all the claims
remaining in the application. Claims 2, 3, 11, 19, 20, and 22 are cancelled.
We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.

Representative Claim
1. A processor comprising:

a plurality of storage locations, wherein each of the plurality of
storage locations is addressable as a speculative register and is configured to
store result data generated during execution of an instruction operation and a
value representing an update for a status/control register (SCR), wherein the
value includes at least an exception encoding, and wherein the exception
encoding encodes an update to a plurality of exception bits in the SCR,
and wherein a first number of bits in the plurality of exception bits is
greater than a second number of bits in the exception encoding, and
wherein the second number of bits is sufficient to encode each possible
combination of one or more exceptions that can occur during execution of
an instruction operation, and wherein some combinations of exceptions are
not possible, and wherein at least one combination includes at least two
exceptions;

a decode circuit coupled to the plurality of storage locations, wherein
the decode circuit is coupled to receive the exception encoding from a first
storage location of the plurality of storage locations responsive to retirement
of a first instruction operation assigned to use the first storage location as a
destination, and wherein the decode circuit is configured to decode the
exception encoding to generate the plurality of exception bits responsive
to retirement of the first instruction; and

the SCR coupled to the decode circuit, wherein the decode circuit is
configured to update the SCR with the plurality of exception bits generated
from the exception encoding.
Appeal 2009-009226
Application 11/281,832

3
Prior Art
Witt US 5,867, 683 Feb. 2, 1999
Chamdani US 6,112,019 Aug. 29, 2000
Takahashi US 6,125,443 Sep. 26, 2000
Hinds US 6,216,222 B1 Apr. 10, 2001
Morrison US 6,223,278 B1 Apr. 24, 2001

John Paul Shen & Mikko H. Lipasti, Modern Processor Design:
Fundamentals of Superscalar Processors, McGraw Hill, Beta Edition, 159-
61 (2002).

Examiner’s Rejections
Claims 1, 9, 10, 16, 17, and 21 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Chamdani, Morrison, and Hinds.
Claims 4, 5, 12, 13, 23, and 24 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Chamdani, Morrison, Hinds, and Witt.
Claims 6, 14, and 25 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Chamdani, Morrison, Hinds, and Takahashi.
Claims 7, 8, 15, and 26 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Chamdani, Morrison, Hinds, Takahashi, and Witt.
Claim 18 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Chamdani, Morrison, Hinds, and Shen.

FINDINGS OF FACT
Morrison
Morrison teaches a scheduler 125 (Fig. 1) that determines when
micro-ops will be executed by a plurality of execution units 130. The micro-
ops are usually executed out of order. An instruction retirement unit (IRU)
135 “retires” the micro-ops when executed properly by the execution units.
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Application 11/281,832

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The IRU 135 (Fig. 2) includes a re-order queue (ROQ) 210, which stores the
floating point micro-ops in the original “program” order and a floating point
status word (FPSW), which indicates whether or not corresponding micro-
ops executed properly. Every floating point instruction logs its status
information in ROQ 210 as it executes in the pipeline. Col. 3, ll. 21-59.
The ROQ 210 maintains the architectural FPSW by updating the
FPSW as the IRU 135 retires the various floating point instructions in
program order. Col. 3, ll. 59-62.

Hinds
Hinds teaches six types of exceptions that may be detected by a
floating point unit, which cause an exception processing tool to be invoked.
To enable the exceptions to be dealt with by the exception processing tool,
information is stored in an exception status register. The information
includes the exception type. Three bits are sufficient to specify the six
exception types. Col. 6, l. 61 - col. 7, l. 15.

PRINCIPLES OF LAW
The allocation of burdens requires that the USPTO produce the factual
basis for its rejection of an application under 35 U.S.C. §§ 102 and 103. In
re Piasecki, 745 F.2d 1468, 1472 (Fed. Cir. 1984) (citing In re Warner, 379
F.2d 1011, 1016 (CCPA 1967)). The one who bears the initial burden of
presenting a prima facie case of unpatentability is the Examiner. In re
Oetiker, 977 F.2d 1443, 1445 (Fed. Cir. 1992).

Appeal 2009-009226
Application 11/281,832

5
ANALYSIS
According to the statement of rejection against claim 1, Morrison at
column 3, lines 59 through 62 teaches essentially all the requirements of the
claimed “decode circuit.” Ans. 5. As we previously noted, Morrison at the
cited text teaches that a re-order queue maintains an architectural floating
point status word (FPSW) by updating the FPSW as an instruction
retirement unit retires the various floating point instructions in program
order.
Further, according to the statement of rejection against claim 1, Hinds
teaches essentially all the requirements of the claimed exception encoding in
text at column 6, line 61 through column 7, line 10. Ans. 6. We note,
however, that claim 1 recites that the “decode circuit” -- which the rejection
deems to be taught by Morrison -- is configured to decode the “exception
encoding” to generate the plurality of exception bits responsive to retirement
of the first instruction. Moreover, Hinds appears to teach uniquely
identifying one of six types of exception by using three bits. That is, two
bits could uniquely identify each of four exceptions, and three bits could
uniquely identify each of eight exceptions, but three bits are necessary to
uniquely identify each of five to eight exceptions. Claim 1 recites, however,
that the encoding bits are sufficient to encode “each possible combination of
one or more exceptions,” wherein “at least one combination includes at least
two exceptions.”
The rejection partly acknowledges Hinds’ shortcomings, by
continuing that the cited references do not “explicitly” disclose that at least
one combination of encoded exception bits includes at least two exceptions.
However, the Examiner contends that “it is well known” in the computer arts
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Application 11/281,832

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that an instruction may cause multiple exceptions, concluding that it would
have been obvious to record two or more exceptions caused by an
instruction. Ans. 7.
In response to Appellants’ arguments that Morrison does not teach a
decoder or “decoding” as claimed, the Examiner submits that the subject
matter in question simply does not meet the requirements for patentability
due to its obvious nature. “Specifically, the concept of storing a value in an
encoded, or reduced-bit, form is incredibly common and the benefits are
well known,” for the purpose of storing more data in a system with storage
limitations. Ans. 16.2
In the Examiner’s view, “claim 1 is simply reciting techniques that are
well known and common and would therefore have been obvious to a person
having ordinary skill in the art.” Ans. 16. The Examiner admits that Hinds
does not teach detecting at least two exceptions for the same instruction
operation, but posits that “it would have been obvious to encode
combinations of at least two exceptions because the purpose of the cited
systems is to maintain correct program state and, in order to do this, a
processor must be able to recover from any exceptions that have occurred,
including those that may have occurred simultaneously.” Id.
We agree with Appellants, essentially for the reasons expressed in the
briefs, the rejection fails to set forth a prima facie case of unpatentability for
the subject matter as a whole of claim 1. In particular, the teachings with

2 The Examiner also alleges (Ans. 15-16) that “decode” is an “incredibly
broad” term and that a decoder may simply output the same values that are
input to it. As Appellants note (e.g., Reply Br. 4), however, the claims recite
specific encoding and decoding, which is not so “incredibly broad” as
passing an input to an output.
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respect to “encoding” and “decoding” that the rejection attributes to
Morrison and Hinds are not supported by the references. Further, the
admitted deficiencies of the references are not remedied by allegations of
what would have been, in general, obvious to the artisan, absent a showing
from pertinent prior art references in support of the allegations.
Each of the other independent claims on appeal (10 and 21) recites
limitations similar to those of claim 1, but is rejected on the same basis as
claim 1. As the additional references applied against dependent claims do
not remedy the basic deficiencies in the rejection against claims 1, 10, or 21,
we cannot sustain the rejection of any claim on appeal.

DECISION
The rejections of claims 1, 4-10, 12-18, 21, and 23-26 under
35 U.S.C. § 103(a) are reversed.

REVERSED

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