Ex Parte LI et al

Patent Trial and Appeal Board

Oct 31, 2012

11618655 (P.T.A.B. Oct. 31, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte DANDAN LI and ARYA BEHZAD
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Appeal 2010-007766
Application 11/618,655
Technology Center 2800
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Before MARC S. HOFF, CARLA M. KRIVAK, and ELENI MANTIS
MERCADER, Administrative Patent Judges.
MANTIS MERCADER, Administrative Patent Judge.

DECISION ON APPEAL

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STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) from the final rejection of
claims 1-27. We have jurisdiction under 35 U.S.C. § 6(b).
We Affirm.

THE INVENTION
Appellants claimed invention is directed to a method and system for
doubling the phase detector comparison frequency for a fractional-N phase-
locked-loop (PLL). See generally Spec. ¶ [001].
Independent claim 1, reproduced below, is illustrative of the subject
matter on appeal.
1. A method for signal processing, the method comprising:
detecting a duty-cycle of a digital reference clock signal utilized
by a frequency doubler for doubling phase-frequency detector (PFD)
comparison rate in a fractional-N phase-locked-loop (PLL)
synthesizer;
generating a reference voltage signal based on said detected
duty-cycle of said digital reference clock signal; and
adjusting said duty-cycle of said digital reference clock signal
based on said generated reference voltage signal when said detected
duty-cycle of said digital reference clock signal is different from a
reference duty-cycle value.

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REFERENCES and REJECTION
The Examiner has rejected claims 1-27 under 35 U.S.C. § 103(a) as
being unpatentable over Merrill (US 6,538,520 B1; filed Mar. 25, 2003) in
view of Wynen (US 6,578,154 B1; filed June 10, 2003) and Wells (US
4,609,881; filed Sept. 2, 1986).
ISSUES
The issues are whether the Examiner erred in finding that the
combination of Merrill, Wynen, and Wells teaches:
1. “detecting a duty-cycle of a digital reference clock utilized by a
frequency doubler,” as recited in claim 1;
2. a “digital reference clock signal is generated from a low slew-
rate reference clock signal,” as recited in claims 3 and 17; and
3. “disabling said generation of said reference voltage signal,” as
recited in claims 11 and 25.
PRINCIPLES OF LAW
There is no requirement that a person of ordinary skill in the art would
have recognized the inherent disclosure at the time of invention, but only
that the subject matter is in fact inherent in the prior art reference. Schering
Corp. v. Geneva Pharm. Inc., 339 F.3d 1373, 1377 (Fed. Cir. 2003).
The Supreme Court stated that “[r]ejections on obviousness grounds
cannot be sustained by mere conclusory statements; instead, there must be
some articulated reasoning with some rational underpinning to support the
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legal conclusion of obviousness.” KSR Int’l Co. v. Teleflex Inc., 550 U.S.
398, 418 (2007) (quoting In re Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006).
An artisan is presumed to possess both skill and common sense. See
KSR, 550 U.S. at 421 (“A person of ordinary skill is also a person of
ordinary creativity, not an automaton.”).
Examined claim terms are given their broadest reasonable meaning
utilizing ordinary usage as such claim terms would be understood by one
skilled in the art by way of definitions and the written description. In re
Morris, 127 F.3d 1048, 1054 (Fed. Cir. 1997).
Our reviewing court states that “the words of a claim ‘are generally
given their ordinary and customary meaning.’” Phillips v. AWH Corp., 415
F.3d 1303, 1312 (Fed. Cir. 2005) (en banc) (internal citations omitted). The
description in the Specification can limit the apparent breadth of a claim in
two instances: (1) where the Specification reveals a special definition given
to a claim term by the patentee that differs from the meaning it would
otherwise possess; and (2) where the Specification reveals an intentional
disclaimer, or disavowal, of claim scope by the inventor. Id. at 1316.
ANALYSIS
Claims 1, 6-10, 14, 16, and 20-24
Appellants first argue that Merrill does not disclose an equalizer 106
“detecting a duty cycle of a digital reference clock signal utilized by a
frequency doubler” (App. Br. 13). The Examiner found that the equalizer
“cannot equalize/restore the duty cycle of a signal without detecting what the
duty cycle of the [signal] is” (Ans. 14). Merrill teaches that the equalizer
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“helps restore the duty cycle of the signal before it enters the second
frequency doubler, and the second equalizer helps restore the duty cycle
before the signal enters the PLL. The increased (quadrupled) reference
frequency allows the PLL to have a smaller feedback divider ratio and
therefore fewer dividers” (col. 1, ll. 51-57) (emphasis added). We find no
error in the Examiner’s determination that the equalizer 106 must detect the
duty cycle of the signal while the duty cycle is being restored, otherwise
there would be no duty cycle to restore. See Schering, 339 F.3d at 1377.
Appellants argue that Merrill’s equalizer 106 detects the duty cycle
after the frequency doubler 104. Appellants explain that the equalizer 106
utilizes the “output” of the frequency doubler 104, and does not detect a duty
cycle “utilized by” a frequency doubler (App. Br. 13). Appellants’ assertion
is not compelling because the Examiner relied on the duty cycle detected by
the equalizer 106, which is utilized by a frequency doubler 108--not the
frequency doubler 104 (Ans. 15).
Appellants further argue that Wynen is not an equalizer, and therefore
not combinable with Merrill (App. Br. 15). The Examiner found that Wynen
teaches a duty cycle correction circuit that provides equalization (uniform
high and low pulses) of the output signal (Ans. 16). Wynen shows the
equalized signal (Figure 4) and recites equal duty cycle ratios (col. 6, ll. 24-
28), where accurate control of the duty cycle provides high clock rates or
lower core voltages (col. 1, ll. 25-35). Thus, Wynen does disclose and
equalizer. We therefore do not agree with Appellants’ argument that Merrill
and Wynen are not combinable. The Examiner has articulated a rational
underpinning for combining Merrill and Wynen, which is to provide an
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equalizer capable of operating at high frequencies and low core voltages
(Ans. 5, ll. 3-8). See KSR, 550 U.S. at 418.
Further, while we agree that Merrill does not teach the specific
circuitry of the equalizer, Merrill nonetheless suggests the use of
conventional circuitry (col. 3, ll. 15-20). A person of ordinary skill in the art
would know to look to a known duty cycle controller, such as Wynen, to
make and use the phase lock loop circuit of Merrill. An artisan is presumed
to possess both skill and common sense. See KSR, 550 U.S. at 421 (“A
person of ordinary skill is also a person of ordinary creativity, not an
automaton.”)
Accordingly, we affirm the Examiner’s rejection of claims 1 and 14,
as well as their dependent claims 6-10, 16, and 20-24, not separately argued
by Appellants.
Claims 2 and 15
Appellants argue that Merrill does not disclose “doubling a frequency
of said digital reference clock signal after said adjusting, using a frequency
doubler” (App. Br. 17). As stated above, the Examiner relied on the duty
cycle detected by the equalizer 106, which is utilized by a frequency doubler
108--not the frequency doubler 104 (Ans. 14). Thus, the frequency doubler
108 doubles the frequency after adjusting by the equalizer 106 (see Fig. 1 of
Merrill).
Accordingly, we affirm the Examiner’s rejection of claims 2 and 15.
Claims 3, 4, 5, 12, 13, 17, 18, 19, 26, and 27
Appellants argue that the combination of Merrill, Wynen, and Wells
does not teach a digital reference clock signal generated from a low slew rate
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reference clock signal (App. Br. 18). The Examiner finds that clock signal
120 is generated from a low slew rate oscillator (Ans. 17; Merrill, see col. 2,
ll. 36-37). The claims are given their broadest reasonable interpretation in
light of the specification. See In re Morris, 127 F.3d 1054. The
Specification does not provide any specific definition of what constitutes a
“low slew-rate” (Spec. ¶ [0020]). We therefore consider a reasonable
interpretation is one such that a crystal oscillator can be considered to have a
low slew rate when compared to other types of oscillators or clock signals.
We further note that the description in the Specification can limit the
apparent breadth of a claim in two instances: (1) where the Specification
reveals a special definition given to a claim term by the patentee that differs
from the meaning it would otherwise possess; and (2) where the
Specification reveals an intentional disclaimer, or disavowal, of claim scope
by the inventor. See Phillips, 415 F.3d at 1316. Appellants’ Specification
provides neither a special definition nor reveals an intentional disclaimer or
disavowal of claim scope.
Therefore, we affirm the Examiner’s rejection of claims 3 and 17, as
well as dependent claims 4, 5, 12, 13, 18, 19, 26, and 27, not separately
argued by Appellants.

Claims 11 and 25
Appellants argue that Wynen does not teach the step of “disabling
said generation of said reference voltage signal” (App. Br. 20).
We do not agree. Claim 11 does not require disabling the generation
of the voltage reference as argued by Appellant, only that it is disabled in
regards to “said detected duty cycle of the digital reference clock signal.”
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The Examiner finds, and we agree, that Wynen teaches disabling the
reference voltage signal based upon the detected duty cycle because once the
duty cycle reaches equilibrium, Vref stops increasing in value, and no
additional charge is added to capacitor 306 (see Ans. 19 and col. 5, ll. 7-12).
The Examiner concludes, and we agree, that Wynen teaches disabling the
reference voltage signal based upon the detected duty cycle because Vref is
generated at a “constant magnitude to maintain a constant voltage that is half
the rail voltage” (Ans. 19, and see Wynen, col. 6, ll. 11-16). Thus, Wynen
teaches that the reference voltage is generated based on the stored charges,
and not upon the detected duty cycle of the digital reference clock, thereby
meeting the claim language of “disabling” the generation of the reference
voltage based on the duty-cycle of the digital reference clock signal.
Therefore, we affirm the Examiner’s rejection of claim 11 and for the
same reason the rejection of claim 25.

CONCLUSION
The Examiner did not err in finding that the combination of Merrill,
Wynen, and Wells teaches:
1. “detecting a duty cycle of a digital reference clock utilized by a
frequency doubler,” as recited in claim 1;
2. a “digital reference clock signal is generated from a low slew
rate reference clock signal,” as recited in claims 3 and 17; and
3. “disabling said generation of said reference voltage signal,” as
recited in claims 11 and 25.

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DECISION
The Examiner’s decision rejecting claims 1-27 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv)(2010).
AFFIRMED
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