Ex Parte Lesot et al

Patent Trial and Appeal Board

Apr 15, 2013

11116893 (P.T.A.B. Apr. 15, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte JEAN-PHILIPPE LESOT and GERARD CHAUVEL
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Appeal 2010-011535
Application 11/116,893
Technology Center 2100
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Before ROBERT E. NAPPI, KRISTEN L. DROESCH, and
PATRICK M. BOUCHER, Administrative Patent Judges.

BOUCHER, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2010-011535
Application 11/116,893
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STATEMENT OF THE CASE
Introduction
Appellants appeal under 35 U.S.C. § 134 from a rejection of claims 1–
7 and 9–25. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

Illustrative Claim
The disclosure relates to an executable load instruction that copies
data from memory to a register and causes an optional check for an error
condition to be performed.
Claim 1 is illustrative and is reproduced below:1
1. A processor, comprising:
an arithmetic logic unit (ALU); and
a plurality of registers coupled to the ALU;
wherein, based on a control bit in a memory access
instruction, said processor executes said instruction by causing
contents of one of the registers to be compared to a
predetermined value and if said contents equals said
predetermined value, said processor causes an exception to be
generated; and
if said contents differs from said predetermined value,
said instruction causes said processor to cause a data value from
memory to be loaded into another of the registers.

References
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:

1 As the Examiner notes, claim 1 is reproduced incorrectly in the Claims
Appendix of Appellants’ Brief (Ans. 3). The text of the claim we consider is
drawn from the Amendment filed November 13, 2009.
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Abbott

US 6,006,321

Dec. 21, 1999
Cupps
Butcher
US 2003/0163666 A1
US 2005/0216711 A1
Aug. 28, 2003
Sep. 29, 2005

Rejections2
The Examiner made the following rejections:
Claims 1–7, 9–21, 23, and 24 stand rejected under 35 U.S.C §103(a)
as unpatentable over Butcher in view of Abbott.3
Claims 22 and 25 stand rejected under 35 U.S.C §103(a) as
unpatentable over Butcher and Abbott and further in view of Cupps.

ANALYSIS
We have reviewed Appellants’ arguments in their Appeal Brief and
Reply Brief, and have reviewed the Examiner’s response to Appellants’
arguments. We disagree with Appellants’ conclusions.

2 While the Appeal Brief also addresses a rejection of claim 16 under 35
U.S.C. §112, ¶1 (App. Br. 7–8), this rejection was withdrawn by the
Examiner (Ans. 3) and is therefore not before us.
3 Separate patentability is not argued for dependent claims 3–7, 9, 11, 12, 14,
15, 18–21, 23, or 24. Although each of these claims is addressed in a
separate paragraph, Appellants merely reference the arguments presented for
one of independent claims 1, 10, or 16 without presenting any additional
arguments to establish separate patentability. We accordingly treat
independent claim 1 as representative for dependent claims 3–7 and 9; treat
independent claim 10 as representative for dependent claims 11, 12, 14, and
15; and treat independent claim 16 as representative for dependent claims
18–21, 23, and 24. Except for our ultimate decision, those dependent claims
are not discussed further herein.
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First Contention: Claims 1, 10, and 16
Appellants contend that the Examiner erred in rejecting claims 1, 10,
and 16 under 35 U.S.C. §103(a) because “[n]o where … does Butcher teach
or suggest anything about what occurs when no ‘exception’ is determined”
(App. Br. 10). We disagree that the Examiner has erred.
Butcher is directed generally to “the handling of exceptions due to
program instructions making reference to null values” (Butcher ¶2). Fig. 3
of Butcher provides “a flow diagram illustrating the processing operations
following a memory access instruction” (¶43). As part of these processing
operations, a comparison is performed between a value read from a base
register and a predetermined null value. If the comparison “results in a non-
match with the null value, then the normal memory access instruction is
executed” (¶43) and if the comparison “results in a match with the null
value, then a null value exception needs to be initiated” (¶44).
In light of this teaching, we disagree with Appellants that “[n]o where
… does Butcher teach or suggest anything about what occurs when no
‘exception’ is determined.” Instead, we agree with the Examiner that
“Butch[er] clearly details what occurs in both cases [when an exception is
determined and when no exception is determined]” (Ans. 12).

Second Contention: Claims 10 and 16
Appellants contend that the Examiner erred in rejecting claims 10 and
16 under 35 U.S.C. §103(a) because “no where does the control bit in
Abbott cause data to be moved between a memory address and another of
the registers” (App. Br. 11). We disagree that the Examiner has erred.
Appellants attack the references individually when the Examiner has,
in fact, relied on the combination of Butcher and Abbott to support the
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rejection under 35 U.S.C. §103(a). The proper test for obviousness is what
the combined teachings of the prior art would have suggested to the
hypothetical person of ordinary skill in the art. In re Keller, 642 F.2d 413,
425 (CCPA 1981). Specifically, “Abbott is not relied upon to teach a
control bit that causes data to be moved between memory and a register.
[The] Examiner only relies on Abbott to teach a control bit” (Ans. 13). We
are not persuaded that the Examiner erred in finding that “it would have
been obvious to one of ordinary skill in the art at the time the invention was
made to incorporate the [control-bit] teaching of Abbott into the teaching of
Butcher to have a control bit capable of disabling the null value check”
(Ans. 7).

Third Contention: Claims 10 and 16
Appellants contend that the Examiner erred in rejecting claims 10 and
16 under 35 U.S.C. §103(a) because the Examiner’s expanded articulation of
a motivation for combining the teachings of Butcher and Abbott relies on an
invalid inherency argument (App. Br. 12, citing Advisory Action, p. 2, ll.
11–14). We disagree that the Examiner has erred.
Contrary to Appellants’ assertion, we discern no reliance on an
inherency rationale in the Examiner’s remarks. Instead, we perceive them to
be a correct response “that an explicit recitation of motivation is not required
to be in the prior art if the knowledge of such motivation would be available
as knowledge to one of ordinary skill in the art” (Ans. 15). See In re Fine,
837 F.2d 1071 (Fed. Cir. 1988). In addition to being unpersuaded that the
Examiner has improperly relied on an inherency rationale, we are also not
persuaded that the Examiner erred in relying on the expressed motivation of
“hav[ing] the option to turn off error checking in conditions where it
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wouldn’t be necessary to do so, such as in a fully tested software
application” (Ans. 15).

Fourth Contention: Claims 1, 10, and 16
Appellants contend that the Examiner erred in rejecting claims 1, 10,
and 16 under 35 U.S.C. §103(a) because “all of the words of Claims 1, 10
and 16 have not been considered in judging the patentability of the claims
against the prior art” (App. Br. 13). Specifically, Appellants “challenge
[the] Examiner’s inherency argument that[] ‘use of a base register value
inherently requires calculation to add the base register value and the index
value to obtain a valid memory address’” (id.). We disagree that the
Examiner has erred.
While Appellants phrase their contention as applying to each of
independent claims 1, 10, and 16, their specific remarks are directed at the
limitation of claim 10 requiring that “said memory location hav[e] an
address based on the first register value” and the limitation of claim 16
requiring that “the memory address be[] calculated using the contents of said
one of the registers” (App. Br. 13). The Examiner correctly observes that
Appellants describe and recite address calculation broadly: “Appellant[s] at
no point ha[ve] provided any specifics as to the calculation of the address,
merely that a value of a single register is used” (Ans. 16). We also note, in
addition to the observations made by the Examiner, that in discussing the
method for checking for null-value exceptions in Fig. 2, Butcher describes
that “[w]hen a null value exception occurs, a branch is made to a memory
location specified by an address held within the configuration coprocessor
register subject to a fixed offset, in this case ‘–4’.” (Butcher ¶42). Butcher
thus clearly contemplates the use of offset values as the Examiner indicates:
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“Butcher makes use of the term ‘base register value’ and in doing so means
that there would be some additional value added to the register value, an
index or offset value” (Ans. 16). We are accordingly unpersuaded that the
Examiner erred in analyzing the relevant limitations of claims 1, 10, and 16.

Fifth Contention: Claims 2, 13, and 17
Appellants contend that the Examiner erred in rejecting claim 2 under
35 U.S.C. §103(a) because the “Examiner has pointed to no teaching in
Abbott where the only mention of use of a single control bit (versus use of
multiple control bits) is programmable in selectively negating [certain]
output bits” (App. Br. 16). Similar contentions are made with respect to the
programmable nature of the control bit for claims 13 (App. Br. 18) and 17
(App. Br. 20). We disagree that the Examiner has erred.
Instead we agree with the Examiner’s analysis that “[t]he control bits
for controlling the system [in Abbott] are by nature dynamic and are
programmable” (Ans. 17, citing Abbott, abs.). “This is further made clearer
in that the control information is supplied by the decoding logic unit[,
whose] output would be based on the instructions that are decoded, which
again means the control bits are programmable by virtue of them being
resulting from instructions” (id.)

Sixth Contention: Claim 14
Appellants contend that the Examiner erred in rejecting claim 1 under
35 U.S.C. §103(a) by relying on Abbott’s disclosure of the use of multiple

4 We address this contention at this point because it is raised inferentially by
Appellants’ expression of their fifth contention, but made more explicitly in
connection with claim 1 in the Reply Brief.
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control bits, with Appellants arguing that “[t]he two limitations [of ‘based on
at least one bit’ and ‘based on a control bit’] are different” (Rep. Br. 5) and
that “Abbott makes it clear that plural control bits are required – NOT ‘a
control bit’, as required by Claim 1” (Rep. Br. 6). We disagree that the
Examiner has erred.
Our reviewing court
has repeatedly emphasized that an indefinite article “a” or “an”
in patent parlance carries the meaning of “one or more” in
open-ended claims containing the transitional phrase
“comprising.” … Unless the claim is specific as to the number
of elements, the article “a” receives a singular interpretation
only in rare circumstances when the patentee evinces a clear
intent to so limit the article…. Under this conventional rule, the
claim limitation “a,” without more, requires at least one.

KCJ Corp. v. Kinetic Concepts, Inc., 223 F.3d 1351, 1356 (Fed.
Cir. 2000) (citations omitted).

As the Examiner emphasizes (Ans. 3–4), the claims use the transitional
phrase “comprising,” and we are unable to discern any clear intent in
Appellants’ specification to limit interpretation of the indefinite article in
any way different than the conventional rule.

Seventh Contention: Claims 22 and 25
Appellants contend that the Examiner erred in rejecting claims 22 and
25 under 35 U.S.C. §103(a) because “Cupps fails to teach or suggest the
above identified deficiencies of any combination of Butcher & Abbot[t] as
applied to Claims 22 & 25” (App. Br. 26). We disagree that the Examiner
has erred.
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Appellants’ contention is derived from their arguments that the
Examiner’s rejections relying on Butcher and Abbott are deficient, and that
Cupps fails to remedy such deficiencies. Since we find that the Examiner
has not erred in relying on Butcher and Abbott for the reasons expressed
supra, we find this contention unpersuasive.

CONCLUSION
On the record before us, we conclude that the Examiner has not erred
in rejecting claims 1–7 and 9–25 under 35 U.S.C. §103(a).

DECISION
The Examiner’s decision rejecting claims 1–7 and 9–25 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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