Ex Parte Lee et al

Patent Trial and Appeal Board

Jan 17, 2013

11618453 (P.T.A.B. Jan. 17, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/618,453 12/29/2006 Jae Gon Lee ICIS-0522 5841
22898 7590 01/18/2013
ISHIMARU & ASSOCIATES LLP
2055 GATEWAY PLACE
SUITE 700
SAN JOSE, CA 95110
EXAMINER
AHMED, SELIM U
ART UNIT PAPER NUMBER
2826
MAIL DATE DELIVERY MODE
01/18/2013 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
________________

Ex parte JAE GON LEE, LEE WEE TEO, and
SEONG-DONG KIM
________________

Appeal 2010-005484
Application 11/618,453
Technology Center 2800
________________

Before ERIC B. CHEN, STANLEY M. WEINBERG, and
JOHN A. EVANS, Administrative Patent Judges.

WEINBERG, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2010-005484
Application 11/618,453

2
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 1-20. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.
Claims 1-5, 10, 11, and 15-20 stand rejected under 35 U.S.C.
§ 103(a) as obvious over Cheng (US 2007/0020866 A1, Jan. 25, 2007) in
view of Sudo (US 2007/0262392 A1, Nov. 15, 2007).
1

Claims 6-9 and 12-14 stand rejected under 35 U.S.C. § 103(a) as
obvious over Cheng in view of Kohyama (US 2006/0231826 A1, Oct. 19,
2006) and Sudo.
2

STATEMENT OF THE CASE
Appellants’ invention relates to an integrated circuit system
employing strained technology having NMOS and PMOS devices. An SiO2
shallow trench isolation (STI) 138 in Si substrate 118 separates NMOS
device 102 and PMOS device 104. The difference in thermal expansion
between the SiO2 and the Si produces strain in PMOS channel 126 and
NMOS channel 110. Although strain in PMOS channel 126 improves
performance, strain in the NMOS channel 110 degrades performance. A
strain suppressing feature 1800 that reduces strain to NMOS channel 110 is
generally rectangular, parallel to the length of NMOS gate 106, in the STI

1
Throughout this opinion, we refer to (1) the Appeal Brief filed May 28,
2009; (2) the Examiner’s Answer mailed October 2, 2010; and (3) the Reply
Brief filed December 2, 2009.
2
Claim 10 depends from claim 6. The Examiner inadvertently grouped
claim 10 with claim 1, instead of with claim 6. The rejection of claim 10
relies upon Sudo for the specific limitations recited in claim 10 as the
Answer explains in detail. Ans. 6-7. The incorrect grouping is therefore
harmless error.
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138, and perpendicular to the direction of the strain. STI 138 is formed
around strain suppressing feature 1800 and is therefore a region of substrate
118 that has not been formed into STI 138. The distance between strain
suppression feature 1800 and NMOS device 102 affects the strain on NMOS
device 102. Because strain increases as the distance increases, strain can be
optimized by adjusting the position of strain suppressing feature 1800
relative to NMOS device 102. See generally Spec. 1:3-4; 5:1-4, 22-25; 13:9-
14:2. Figs. 1, 18.
Independent claim 1 is illustrative with key disputed limitations
emphasized:
1. A method of manufacture for an integrated circuit system
comprising:
providing a substrate with a PMOS device and an NMOS device;
forming an NMOS shallow recess within the substrate;
forming a PMOS recess within the substrate;
forming a strain inducing layer over the PMOS recess;
forming a strain suppressing feature adjacent the NMOS device; and
forming a first dielectric layer over the NMOS device and a second
dielectric layer over the PMOS device.

The Examiner finds that Cheng discloses every recited feature of
representative claim 1 except for forming a strain suppressing feature
adjacent the NMOS device; but finds that Sudo’s element 101 isolated by
element 130 adjacent to its NFET discloses a structure that is identical to
Appellants’ strain suppressing feature. Ans. 4:13-18.
Appellants contend that Sudo’s elements 101 and 130 do not disclose
a strain suppressing feature adjacent an NMOS device, but instead disclose
an STI layer 130 that prevents stray current from flowing into and out from
adjacent NFET and PFET devices. App. Br. 11:20-23.
Appeal 2010-005484
Application 11/618,453

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ISSUE
Under § 103, has the Examiner erred by finding that Sudo teaches a
strain suppressing feature adjacent an NMOS device?

ANALYSIS
THE OBVIOUSNESS REJECTION OVER CHENG IN VIEW OF SUDO
Claims 1, 3, 4, 11, and 15-20
We begin by construing the key disputed limitation of claim 1 which
recites, in pertinent part, “a strain suppressing feature adjacent the NMOS
device.”
Appellants’ Specification discloses a “STI [shallow trench isolation]
138 is made of silicon dioxide (“SiO2”) and the substrate 118 is made of Si.”
Spec. 13:12-13; Fig. 18. A “strain suppressing feature 1800 [is] generally
rectangular [and] parallel to the length of the NMOS gate 106.” Spec.
13:18-20. The STI 138 is “formed around the strain suppressing feature
1800. Thus . . . the strain suppressing feature 1800 is a region of the
substrate 118 that has not been formed into the STI 138, but instead remains
unaltered by the STI-forming process.” Spec. 13:27-30. Thus, under the
broadest reasonable interpretation consistent with the Specification, the
“strain suppressing feature” 1800 is defined as a rectangular feature that is
parallel to the length of the NMOS gate 106 comprising a region of the
silicon substrate 118 that has not been formed into the STI 138 so that the
STI 138 is formed around the strain suppressing feature 1800.
The Examiner finds that Sudo’s Figs. 1 and 2 show rectangular silicon
element 101 isolated by (i.e., surrounded by) STI 130 and adjacent to Sudo’s
NFET. Ans. 4:15-18; 14:17-15:1. The Examiner therefore finds that Sudo’s
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Figs. 1 and 2 depict a structure that is identical to Appellants’ strain
suppressing feature 1800. Ans. 4:15-18; 14:20-15:1.
Appellants argue that Sudo’s elements 101 and/or 130 do not disclose
an “intent of suppressing strain” because Sudo’s elements 101 and 130 are
formed “with the intent to prevent stray current from flowing between
adjacent NFET and PFET devices.” App. Br. 11:31-35. Purported intent or
lack of intent, however, is not indicative of structural differences.
Appellants also argue that (1) a skilled person would know that
forming STI layer 130 for purposes of electrical isolation is not the
equivalent of forming a strain suppressing feature (App. Br. 13:21-23); and
(2) “Sudo’s silicon structure 101 may not be appropriately designed and/or
located to suppress strain.” Reply Br. 5:28-29. These latter arguments are
not persuasive because Appellants present no evidence in support of them.
Appellants also present a number of arguments regarding the position
of Sudo’s element 101 within Sudo’s device based upon what a skilled
person purportedly would know regarding the relationship of the distance
between a strain suppressing feature and its intended target. App. Br. 13:23-
25; Reply Br. 3:11-14; Reply Br. 4:5-8; Reply Br. 5:18-29. These
arguments are not persuasive because claim 1 does not recite the position of
the strain suppressing feature.
Because Appellants have not persuasively countered the Examiner’s
comparison of Sudo’s structure to Appellants’ structure, we agree with the
Examiner’s finding that Sudo’s structure is identical to Appellants’ structure.
Based on the Examiner’s finding of Sudo’s identical structure, the
Examiner concludes that Sudo’s identical structure is capable of serving as a
strain suppressing feature and that it is reasonable to predict that Sudo’s
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structure is capable of serving as a strain suppressing feature. Ans. 15:1-4.
Appellants argue that Sudo does not inherently teach a strain suppressing
feature (App. Br. 12:1-21) and does not enable the claimed limitation
because Sudo does not teach the critical location of the strain suppressing
feature (Reply Br. 4:8-16; 5:18-30). As we have indicated, claim 1 does not
recite a location of the strain suppressing feature.
In addition, as we have found, Sudo’s structure is identical to
Appellants’ structure. The inherent properties of prior art elements need not
be disclosed in the prior art. See In re Woodruff, 919 F.2d 1575, 1577-78
(Fed. Cir. 1990) (obviousness rejection affirmed where using claimed
elements in the manner suggested by the prior art necessarily resulted in
claim-recited effect); see also In re Baxter Travenol Labs., 952 F.2d 388,
392 (Fed. Cir. 1991) (“Mere recognition of latent properties in the prior art
does not render nonobvious an otherwise known invention.”).
Once a prima facie case of obviousness has been established, the
burden shifts to the Appellants to prove that the prior art product does not
necessarily or inherently possess the characteristics of the claimed product.
See In re Best, 562 F.2d 1252, 1255 (CCPA 1977):
Where, as here, the claimed and prior art products are identical
or substantially identical, or are produced by identical or
substantially identical processes, the PTO can require an
applicant to prove that the prior art products do not necessarily
or inherently possess the characteristics of his claimed product.
[citation omitted] Whether the rejection is based on ‘inherency’
under 35 U.S.C. § 102, on ‘prima facie obviousness’ under 35
U.S.C. § 103, jointly or alternatively, the burden of proof is the
same, and its fairness is evidenced by the PTO’s inability to
manufacture products or to obtain and compare prior art
products.

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Appellants have not presented any evidence in support of their burden of
proof.
For the reasons we have outlined above, we conclude that Appellants
have not proven that Sudo’s device is different from their claimed device.
3

We are therefore not persuaded that the Examiner erred in rejecting
(1) representative claim 1; (2) claim 11 for similar reasons; and (3) claims 3,
4, and 15-20 not separately argued with particularity.
Accordingly, we will sustain the Examiner’s rejection of claims 1, 3,
4, 11, and 15-20.
Claim 2
The Examiner finds that the limitations of claim 2 are taught by
Cheng’s recessed surfaces 326 and 328 in Cheng’s Fig. 19. Ans. 6. In
response to Appellants’ counter-arguments, the Examiner provides
additional support for the Examiner’s findings. Ans. 16-17, 20:8-21:5.
Appellants, however, do not explain why the Examiner’s findings are
incorrect. Instead, Appellants refer to their own device (Reply Br. 7:21-24)
and contend that the Examiner’s interpretation of Cheng would result in
reducing device performance. Reply Br. 7:24-27.

3
Appellants also argue that the Examiner does not teach or suggest how
Sudo’s shallow trench oxide structure 130 and silicon regions 101 can be
incorporated into Cheng. Reply Br. 6-7. This argument has been made for
the first time in the Reply Brief. “[T]he reply brief [is not] an opportunity to
make arguments that could have been made in the principal brief on appeal
to rebut the Examiner’s rejections, but were not.” Ex parte Borden, 93
USPQ2d, 1473, 1474 (BPAI 2010) (informative). “[A]n issue not raised by
an appellant in its opening brief . . . is waived.” Optivus Tech., Inc. v. Ion
Beam Appl’ns. S.A., 469 F.3d 978, 989 (Fed. Cir. 2006) (citations and
quotations marks omitted).

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Although the claims are interpreted in light of the specification,
limitations from the specification are not read into the claims. In re Van
Geuns, 988 F.2d 1181, 1184 (Fed. Cir. 1993). In addition, Appellants have
not provided any evidence supporting their reduced performance assertion.
We are therefore not persuaded that the Examiner erred in rejecting
claim 2.
Accordingly, we will sustain the Examiner’s rejection of claim 2.
Claims 5 and 18
In the January 6, 2009 Final Rejection of claims 5 and 18, the
Examiner rejected these claims based upon column 6, lines 7-10 of Cheng,
this cited portion of Cheng being in paragraph 0031. See Final Rej. pp. 4, 6.
In the Answer, the Examiner finds that the entire paragraph 0031, not just
column 6, lines 7-10, teach the recited limitations. Ans. 6, 18. For example,
Cheng ¶ 0031, ll. 5-8 states:
“a second portion 1502 over the nMOS region [provides] a
tensile stress to the channel of the nMOS device. In other
embodiments, entire CESL 150 provides a tensile stress.

Appellants do not persuasively rebut the Examiner’s findings because they
do not explain why the entire paragraph 0031 of Cheng fails to support the
Examiner’s findings. Reply Br. 8:11-26. Instead, Appellants quote a
different part of Cheng, ¶ 0033 (Reply Br. 8:16-18), and seek to incorporate
part of their specification into the claims, which is not permissible. Reply
Br. 8:19-26. See In re van Geuns, supra.
We are therefore not persuaded that the Examiner erred in rejecting
claims 5 and 18.
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Accordingly, we will sustain the Examiner’s rejection of claims 5 and
18.
Claims 10 and 20
Even though Appellants recognize that the Examiner did not group
claim 10 with claim 6 as the Examiner should have done (App. Br. 16:7-10;
Reply Br. 10:3-6, 15-18) (see footnote 2, supra), Appellants nevertheless
argue claims 10 and 20 together in the section of their Appeal Brief and
Reply Brief that discusses the Cheng/Sudo rejection, rather than the
Cheng/Sudo/Kohyama rejection. App. Br. 16-17; Reply Br. 9-10.
Representative claim 10, which depends from claim 6, recites
“forming the strain suppressing features includes forming the strain
suppressing feature within a shallow trench isolation.” The Examiner finds
that this limitation is found in Sudo. Ans. 6:22-7:2.
Appellants first contend that the Cheng/Sudo combination does not
teach this limitation because Sudo does not teach a strain suppressing
feature. App. Br. 16:22-26. However, as discussed above, Sudo does, in
fact, teach a strain suppressing feature.
Appellants next contend that the Cheng/Sudo combination does not
teach the limitations of claim 10 because Cheng/Sudo does not teach claim
6’s limitation “forming a PMOS shallow recess and an NMOS shallow
recess.” App. Br. 16:27-29. But, Appellants do not explain why the
Examiner’s initial analysis incorrectly finds that the references teach this
limitation in claim 6. Compare Ans. 10:6-7 with App. Br. 17:4-8.
Secondly, even though the Examiner also refers not only to Cheng’s Figs.
13a and 19, but also to Cheng’s paragraphs 0022 and 0037 (Ans. 21:3),
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Appellants discuss only Figs. 13a and 19. We find the Examiner’s reliance
on all of the cited parts of Cheng to be reasonable.
We are therefore not persuaded that the Examiner erred in rejecting
claim 10 and claim 20 not separately argued with particularity.
Accordingly, we will sustain the Examiner’s rejection of claims 10
and 20.

THE OBVIOUSNESS REJECTION OVER
CHENG IN VIEW OF KOHYAMA AND SUDO
Claim 6
Appellants contend that the cited references do not teach claim 6’s
recitation of “forming a strain suppressing feature adjacent the NMOS
device.” App. Br. 18. Since the contested claim 6 limitation is identical to
the contested claim 1 limitation, and since Appellants’ arguments regarding
claim 6 are substantially the same as their arguments regarding claim 1
(compare App. Br. 11:19-14:18 with App. Br. 18:29-21:21 and compare
Reply Br. 5:11-23; 6:15-17 with Reply Br. 11:17-27), we agree with the
Examiner’s rejection of claim 6 for the same reasons we discussed above
regarding the Examiner’s rejection of claim 1.
In the context of discussing the rejection of claim 10 (which depends
from claim 6), Appellants contend that the cited prior art does not teach
claim 6’s recitation: “forming a PMOS shallow recess and an NMOS
shallow recess. App. Br. 16:27-29. However, in the course of discussing
the Examiner’s rejection of claim 6, Appellants do not explain why the
Examiner’s findings are incorrect regarding “forming a PMOS shallow
recess and an NMOS shallow recess.” Compare Ans. 10:6-7 with App. Br.
17:4-8. We find the Examiner’s reliance of Cheng to be reasonable.
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We are therefore not persuaded that the Examiner erred in rejecting
claim 6.
Accordingly, we will sustain the Examiner’s rejection of claim 6.
Claims 7-9 and 12-14
Method claim 7 recites the PMOS and NMOS shallow recesses are
formed to a depth of “about 30 nanometers to about 60 nanometers.”
Apparatus claim 13 contains a similar limitation. The Examiner finds that
Kohyama teaches a thickness range of 15-25 nm and concludes that it would
have been obvious to form shallow thickness from 30 nm to about 60 nm
through routine experimentation of the etch chemistry and parameters
because it is well known in the semiconductor fabrication process to
optimize the etch thickness of a parameter with a technology using design of
experiment technique to meet certain product specific performance and
reliability. Ans. 12:8-13. Moreover, the Examiner finds that there is no
evidence indicating the ranges of the height of the claimed thickness is
critical or that any unexpected results arise from them. Ans. 12:14-19.
Appellants do not dispute the Examiner’s findings or conclusions
above based upon those findings. App. Br. 21:25-22:20; Reply Br. 11-12.
Instead, Appellants argue Kohyama separately. One cannot show
nonobviousness by attacking references individually where the rejections are
based on combinations of references. See In re Keller, 642 F.2d 413, 426
(CCPA 1981); In re Merck & Co., Inc., 800 F.2d 1091, 1097 (Fed. Cir.
1986).
We are therefore not persuaded that the Examiner erred in rejecting
(1) representative claim 7; (2) claim 13 for similar reasons; and (3) claims 8,
9, 12, and 14 not separately argued with particularity.
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Accordingly, we will sustain the Examiner’s rejection of claims 7-9
and 12-14.

CONCLUSION
Under § 103, the Examiner did not err in rejecting claims 1-20.

DECISION
The Examiner’s decision rejecting claims 1-20 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1). See 37 C.F.R.
§ 1.136(a)(1)(iv) (2010).

AFFIRMED

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