Ex Parte Lee

Patent Trial and Appeal Board

Sep 2, 2016

13010360 (P.T.A.B. Sep. 2, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
13/010,360 01/20/2011 Jong-Ho LEE
23413 7590 09/07/2016
CANTOR COLBURN LLP
20 Church Street
22nd Floor
Hartford, CT 06103
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
ZPL0047USP 2548
EXAMINER
SENGDARA,VONGSAVANH
ART UNIT PAPER NUMBER
2829
NOTIFICATION DATE DELIVERY MODE
09/07/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
usptopatentmail@cantorcolbum.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte JONG-HO LEE
Appeal2014-005353
Application 13/010,3 60
Technology Center 2800
Before TERRY J. OWENS, GEORGE C. BEST, and
N. WHITNEY WILSON, Administrative Patent Judges.
OWENS, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
The Appellant appeals under 35 U.S.C. § 134(a) from the Examiner's
rejection of claims 1, 6, and 9-12. We have jurisdiction under
35 U.S.C. § 6(b).
The Invention
The Appellant claims a transistor. Claim 1 is illustrative:
1. A pillar-type field effect transistor having low leakage
current, comprising:
a substrate;
a semiconductor pillar formed substantially perpendicular
to the substrate, the semiconductor pillar being elongated in a
direction substantially perpendicular to the substrate and
having a length substantially perpendicular to the substrate,
the semiconductor pillar forming along the length of the
Appeal2014-005353
Application 13/010,3 60
Negoro
Chau
Forbes
semiconductor pillar a source region at one end thereat: a
drain region at the other end thereof, and a semiconductor
body between the source region and the drain region;
a gate insulating layer formed around the semiconductor
pillar along the length thereof;
a gate electrode formed around the gate insulating layer,
the gate electrode being divided into a first gate electrode and
a second gate electrode along the length of the semiconductor
pillar,
wherein one of the first gate electrode and the second
gate electrode is a source-side gate electrode, the other one
thereof is a drain-side gate electrode electrically connected to
the source-side gate electrode, and the drain-side gate
electrode has a work function smaller than that of the source-
side gate electrode to thereby reduce a gate-induced-drain
leakage.
The References
US 2004/0183119 Al
US 2007 /0034972 A 1
US 2007/0228491 Al
The Rejections
Sep.23,2004
Feb. 15,2007
Oct. 4, 2007
The claims stand rejected under 35 U.S.C. § 103 as follows: claims 1,
6, 9, 10, and 12 over Forbes in view ofNegoro and claim 11 over Forbes in
view ofNegoro and Chau.
OPINION
We reverse the rejections. We need address only the sole independent
claim, i.e., claim 1. 1
Forbes discloses a pillar-type field effect transistor (603) comprising a
substrate doped to form a conductive line ( 609), a semiconductor pillar
1 The Examiner does not rely upon Chau for any disclosure that remedies the
deficiency in the references applied to the independent claim (Ans. 10-12).
2
Appeal2014-005353
Application 13/010,3 60
(vertical sublithographic channel 604), between source/drain regions (606,
607), a gate insulating layer ( 608) surrounding the semiconductor pillar, and
a gate electrode (605) around the gate insulating layer (iJ 38; Fig. 6). The
transistor provides low sub-threshold leakage in complementary metal oxide
semiconductor circuits (iJ 10).
Negoro discloses a metal oxide semiconductor transistor comprising a
semiconductor substrate (1) with a channel region (19) between source (23s)
and drain (23d) regions and, over the channel region, a gate electrode (21)
having a source side region (21 s) with a work function larger than that of the
drain side region (21 d) such that saturation current can be constant and
A performance (ampere/volt) can be improved (Abstract; iii! 43, 46, 51-54;
Fig. 4B).
Setting forth a prima facie case of obviousness requires establishing
that the applied prior art would have provided one of ordinary skill in the art
with an apparent reason to modify the prior art to arrive at the claimed
invention. See KSR Int'! Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007).
The Examiner asserts that "the teaching of N egoro is relevant to that
of Forbes because the concept of gate taught by Negoro is relevant to the
teaching of Forbes for the benefit taught by Negoro such as having a
threshold voltage of the source side region of the MOS transistor higher than
that of the drain side region in a direction of the channel region so that a
saturation drain current can be constant and a lambda performance can be
improved" (Ans. 6) and that "the gate electrode features [of] Negoro is [sic,
are] the same as the gate features of the appellant[' s] claimed invention.
Therefore, the gate of Forbes can be modified to have the gate electrode
features [of] Negoro" (id.).
3
Appeal2014-005353
Application 13/010,3 60
The Examiner's mere assertions that Negoro's gate concept is relevant
to Forbes and that Forbes can be modified to have N egoro' s gate electrode's
features do not address the differences between Forbes' and Negoro's
transistors and establish that, regardless of those differences, one of ordinary
skill in the art would have had an apparent reason to modify Forbes'
transistor to arrive at the Appellant's claimed transistor. Hence, we reverse
the rejections.
DECISION/ORDER
The rejections under 35 U.S.C. § 103 of claims 1, 6, 9, 10 and 12 over
Forbes in view ofNegoro and claim 11 over Forbes in view ofNegoro and
Chau are reversed.
It is ordered that the Examiner's decision is reversed.
REVERSED
4