Ex Parte Lee

Patent Trial and Appeal Board

Mar 23, 2016

12781532 (P.T.A.B. Mar. 23, 2016)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
12/781,532 05/17/2010 Jeong Ho LEE 10011.009500 (P3407) 2915
61506 7590 03/23/2016
OKAMOTO & BENEDICTO LLP
P.O. BOX 641330
SAN JOSE, CA 95164
EXAMINER
AMSDELL, DANA
ART UNIT PAPER NUMBER
3627
MAIL DATE DELIVERY MODE
03/23/2016 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte JEONG HO LEE
____________

Appeal 2013-008506
Application 12/781,5321
Technology Center 3600
____________

Before HUBERT C. LORIN, MATTHEW S. MEYERS, and ROBERT J.
SILVERMAN, Administrative Patent Judges.

SILVERMAN, Administrative Patent Judge.

DECISION ON APPEAL

STATEMENT OF THE CASE
The Appellant appeals under 35 U.S.C. § 134(a) from the Examiner’s
decision rejecting claims 1–12. We have jurisdiction under 35 U.S.C.
§ 6(b).
SUMMARY OF DECISION
We AFFIRM.

1 According to the Appellant, the real party in interest is KLA-Tencor
Corporation. Appeal Br. 2.

Appeal 2013-008506
Application 12/781,532

2
ILLUSTRATIVE CLAIM
1. A method for run-time correction of defect locations
on a substrate during defect review, the method comprising:
loading the substrate into a stage of a review apparatus,
the review apparatus comprising a source for generating an
electron beam, deflectors configured to scan the electron beam
over a field of view, electron lenses for focusing the electron
beam onto a surface of a substrate being reviewed, a detector
for detecting electrons from the substrate, and electronic control
and image analysis circuitry;
receiving coordinates for the defect locations on the
substrate as detected by an inspection system;
sorting and grouping the defect locations by the
electronic control and image analysis circuitry so as to provide
a sequence of groups of defect locations and a sequence of the
defect locations within each group;
determining at least one local reference site in proximity
to each group of defect locations by the electronic control and
image analysis circuitry; and
using the local reference site(s) to determine, by the
electronic control and image analysis circuitry, a positional
offset for the defect locations in each group.
THE REJECTION
Claims 1–12 are rejected under 35 U.S.C. § 102(b) as anticipated by
Nakasuji et al. (“Nakasuji”) (US 2002/0130262 A1, published September
19, 2002). Final Action 2–3.
FINDINGS OF FACT
We rely on the Examiner’s findings stated in the Answer. Additional
findings of fact may appear in the Analysis below.

Appeal 2013-008506
Application 12/781,532

3
ANALYSIS
Pursuant to 37 C.F.R. § 41.37(c)(1)(iv), “[t]he arguments” in the
Appeal Brief “shall explain why the examiner erred as to each ground of
rejection contested by appellant.” Contrary to 37 C.F.R. § 41.37(c)(1)(iv),
the Appellant has stated simply, and without further explanation, that
Nakasuji does not “disclose” (Appeal Br. 6) or “teach” (id. at 7–9) the
following limitation of claim 1 (id. at 12, Claims App.):
sorting and grouping the defect locations by the electronic
control and image analysis circuitry so as to provide a sequence
of groups of defect locations and a sequence of the defect
locations within each group.
The Appellant’s mere allegation that Nakasuji suffers from this supposed
shortcoming does not amount to any substantive challenge to the Examiner’s
reasoning. See 37 C.F.R. § 41.37(c)(1)(iv) (“A statement which merely
points out what a claim recites will not be considered an argument for
separate patentability of the claim.”)
Nonetheless, the Examiner’s rejection of claim 1 is sustained because
Nakasuji describes the claimed subject matter, including the limitation
identified by the Appellant.
The Appellant acknowledges that the claim limitation at issue has a
broad scope. According to the Appellant (Reply Br. 4):
The meaning of a sequence of groups and a sequence of defect
locations within each group are plain to one of ordinary skill in
the art. The plain meaning of a sequence of groups refers to a
sequential ordering of the groups, and the plain meaning of a
sequence of defect locations within each group clearly refers to
a sequential ordering of the defect locations within each group.
Appeal 2013-008506
Application 12/781,532

4
Therefore, according to the claim language, the grouping of defect locations,
the sequencing of the groups defined thereby, and the sequencing of defect
locations within each group may be undertaken on any basis.
Accordingly, as the Examiner explained (Final Action 4; Answer 4–
5), Nakasuji discloses the grouping of defect locations, according the type of
defect identified, and forming a sequence of these groups. See Nakasuji,
¶¶ 65, 351, 361–363, claim 38. For example, Nakasuji discloses identifying
a portion of a wafer substrate that differs from a reference image and
grouping such portions according to the type of defect identified at each
location, thus defining a sequence of the identified defect groups. Id. at
¶ 360 (“The different portion is considered as a pattern defect. The pattern
defect may be classified into such defect groups including at least short-
circuit, disconnection, convex, chipping, pinhole and isolation.”). See also
id. at claim 38.
In addition, as set forth by the Examiner (Final Action 4; Answer 4–
5), Nakasuji discloses classifying certain defects according to size (see, e.g.,
Nakasuji ¶ 361, claim 38), thereby defining a sequence within each of the
corresponding defined defect groups. To further emphasize the formation of
the sequence of groups of defect locations and the sequences within each
such group, Nakasuji discloses additional processing. For example, “the
classification result is stored in the inspection database” “[a]fter the defect
determination and the classification thereof regarding to the specified
inspection point having been completed” and “a density and/or a yield for a
total defect, for each classified defect, and for each defect distinguished by
size is calculated for each chip or wafer,” which also “may be stored in the
inspection database.” Nakasuji ¶¶ 362–363.
Appeal 2013-008506
Application 12/781,532

5
The Appellant’s remark in the Reply Brief, to the effect that “a defect
‘type or size’ per Nakasuji clearly does not read on the ‘defect locations’ per
the claimed invention” (Reply Br. 5), was not raised in the Appeal Brief and
thus will not be considered for purposes of this appeal. 37 C.F.R.
§ 41.41(b)(2). Nevertheless, the Appellant’s remark is unpersuasive because
the defect types and sizes identified in Nakasuji are all bound to the
particular locations of the substrate being inspected. See, e.g., Nakasuji at
¶ 360.
Accordingly, the Appellant has not pointed out any error in the
Examiner’s analysis, such that the rejection of claim 1 is sustained.
Because the Appellant has not set forth any separate or additional
position, in regard to claims 2–12 (Appeal Br. 9–10; Reply Br. 5), the
Examiner’s rejection of those claims is also sustained.

DECISION
We AFFIRM the Examiner’s decision rejecting claims 1–12.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).

AFFIRMED