Ex Parte Lee

Patent Trial and Appeal Board

Sep 13, 2016

13486387 (P.T.A.B. Sep. 13, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/486,387 06/01/2012
74712 7590 09/15/2016
Muir Patent Law, PLLC
P.O. Box 1213
9913 Georgetown Pike, Suite 200
Great Falls, VA 22066
FIRST NAMED INVENTOR
Jin-YubLee
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
SAM-llOB 1635
EXAMINER
VERBRUGGE, KEVIN
ART UNIT PAPER NUMBER
2132
NOTIFICATION DATE DELIVERY MODE
09/15/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
pto@muirpatentconsulting.com
eofficeaction@appcoll.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte JIN-YUB LEE
Appeal2015-003197 1
Application 13/486,3872
Technology Center 2100
Before ST. JOHN COURTENAY III, THU A. DANG, and
LARRY J. HUME, Administrative Patent Judges.
HUME, Administrative Patent Judge.
DECISION ON APPEAL
This is a decision on appeal under 35 U.S.C. § 134(a) from the Final
Rejection of claims 10-39. Appellant has canceled claims 1-9. Claims 32-
36 are objected to, and indicated as being allowable if rewritten in
independent form. Final Act. 11. We have jurisdiction under 35 U.S.C.
§ 6(b ).
We AFFIRM.
1 We note the Decision mailed June 8, 2015 in Appeal No. 2013-001196 of
related Appl. Ser. No. 11/874,821 reversed the Examiner's rejections.
2 According to Appellant, the real party in interest is Samsung Electronics
Co. Ltd. App. Br. 3.
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Application 13/486,387
STATEMENT OF THE CASE3
The Invention
Appellants' disclosed and claimed invention "generally relates to
nonvolatile flash memories and more specifically, to flash memories for
reliable page copy operations with error correcting functions and their
methods of operating therein." Spec. 1, 11. 11-13 ("Field of the Invention").
Exemplary Claim
Claim 10, reproduced below, is representative of the subject matter on
appeal (emphasis added to contested limitation):
10. A memory system comprising:
a memory cell array comprising a plurality of pages of
non-volatile memory cells, each page configured to store a page
of data;
a page buffer responsive to a copy-back program
operation to copy a source page of data stored in a first page of
the memory array to a second page of the memory array, the
page buffer configured to latch and output the source page of
data read from the first page of the memory cell array, and
configured to write an error corrected page to the second page
of the memory cell array in response to the copy-back program
operation, the page buffer comprising sensing logic configured
to sense the source page from the memory cell array and a
latching unit having a plurality of latches configured to store
and output the source page supplied from the sensing logic;
an error correction circuit configured to receive the
source page from the page buffer, to detect an error of the
3 Our decision relies upon Appellant's Appeal Brief ("App. Br.," filed
Oct. 21, 2014); Reply Brief ("Reply Br.," filed Jan. 20, 2015); Examiner's
Answer ("Ans.," mailed Nov. 18, 2014); Final Office Action ("Final Act.,"
mailed Mar. 7, 2014); and the original Specification ("Spec.," filed
June 1, 2012).
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source page, to correct the error of the source page to obtain the
error corrected page, and to transfer the error corrected page to
the page buffer; and
a column decoder configured to transfer the source page
to the error correction circuit, the column decoder comprising at
least two column gates configured to couple the latching unit
and the input/output lines in response to a column address,
wherein the error correction circuit is configured to
transfer the error corrected page to the page buffer prior to the
page buffer writing to the second page of the memory cell array
in response to the copy-back program operation, thereby
preventing the writing of the source page of data with the error
to the second page of the memory cell array.
Prior Art
The Examiner relies upon the following prior art as evidence in
rejecting the claims on appeal:
Conley et al. ("Conley") US 6,266,273 B 1 July 24, 2001
T p.p. ("T p.p. I 1 ') Q 11 \
_L....JVV \ _L....JVV _._ ._, \J j US 7,296,128 B2 Nov. 13, 2007
Lee ("Lee '030") US 2008/0163030 Al July 3, 2008
Rejections on Appeal4
RI. Claims 10-39 stand rejected on the ground of nonstatutory
obviousness-type double patenting (OTDP) as being unpatentable over
claims 1-20 of Lee '128. Ans. 2; Final Act. 3.
4 While indicated as being allowable if rewritten in independent form in the
Final Rejection (Final Act. 11 ), we note claims 32-36 stand rejected under
Rejections RI and R2, detailed herein. See Final Act. 3, 4; Ans. 2.
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R2. Claims 10-39 stand provisionally rejected on the ground of
nonstatutory OTDP as being unpatentable over claims I I, I8, 2I, 27, 39, 40,
42--46, 48, and 5I-53 of copending Lee '030. Ans. 2; Final Act. 4.
R3. Claims I0-3 I and 37-39 stand rejected under 35 U.S.C.
§ I03(a) as being obvious over Conley. Ans. 2; Final Act. 5.
CLAIM GROUPING
Based on Appellant's arguments (App. Br. IO-I9), we decide the
appeal of obviousness Rejection R3 of claims I 0-3 I and 37-39 on the basis
of representative claim I0. 5 We address OTDP Rejections RI and R2, infra.
ISSUES AND ANALYSIS
In reaching this decision, we consider all evidence presented and all
arguments actually made by Appellant. We do not consider arguments that
Appellant could have made but chose not to make in the Briefs, and we
deem any such arguments waived. 37 C.F.R. § 41.37(c)(l)(iv).
We agree with particular arguments advanced by Appellant with
respect to OTDP Rejections RI and R2 of claims I0-39 for the specific
reasons discussed below. However, we disagree with Appellant's arguments
with respect to§ I03 Rejection R3 of claims I0-3 I and 37-39, and we
incorporate herein and adopt as our own: (I) the findings and reasons set
forth by the Examiner in the action from which this appeal is taken, and
(2) the reasons and rebuttals set forth in the Examiner's Answer in response
to Appellant's arguments. We incorporate such findings, reasons, and
5 "Notwithstanding any other provision of this paragraph, the failure of
appellant to separately argue claims which appellant has grouped together
shall constitute a waiver of any argument that the Board must consider the
patentability of any grouped claim separately." 3 7 C.F .R. § 4 I .3 7 ( c )(I )(iv).
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rebuttals herein by reference unless otherwise noted. However, we highlight
and address specific findings and arguments regarding claim I 0 for
emphasis as follows.
I. OTDP Rejection RI of Claims I 0---39
Issue 1
Appellant argues (Reply Br. 4) the Examiner's OTDP Rejection RI of
claims I 0---39 under the judicially-created doctrine of obviousness-type
double patenting (OTDP) over claims I-20 of U.S. Patent No. 7,296,I28 has
been rendered moot. These contentions present us with the following issue:
Was OTDP Rejection RI rendered moot by the filing of a Terminal
Disclaimer on January I6, 20I5?
Analysis
We find the filing and entry of the Terminal Disclaimer on
January 16, 2015 before the filing of the Reply Brief on January 20, 2015
rendered OTDP Rejection RI moot. Therefore, OTDP rejection RI is no
longer before us on appeal.
2. OTDP Rejection R2 of Claims I 0---39
Issue 2
Appellant argues (Reply Br. 4) the Examiner's OTDP Rejection R2 of
claims I 0---39 under the judicially-created doctrine of obviousness-type
double patenting (OTDP) over claims I I, I8, 2I, 27, 39, 40, 42-46, 48, and
5I-53 of copending Application No. I 1/874,82I has been rendered moot.
These contentions present us with the following issue:
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Was provisional OTDP Rejection R2 rendered moot by the filing of a
Terminal Disclaimer on January 16, 2015?
Analysis
We find the filing and entry of the Terminal Disclaimer on
January 16, 2015 before the filing of the Reply Brief on January 20, 2015
rendered OTDP Rejection R2 moot. Therefore, OTDP rejection R2 is no
longer before us on appeal.
3. § 103 Rejection R3 of Claims 10-31and37-39
Issue 3
Appellant argues (App. Br. 10-19; Reply Br. 4--7) the Examiner's
rejection of claim 1 under 35 U.S.C. § 103(a) as being obvious over Conley
1s m error. These contentions present us with the following issues:
(a) Did the Examiner err by engaging in impermissible hindsight in
combining the cited prior art to teach or suggest the memory system of
claim 1 O?
(b) Did the Examiner err in finding Conley teaches or suggests a
memory system that includes, inter alia, a page buffer," as recited in
independent claim 1 O?
Analysis
Issue 3(a)
Appellant contends,
the Examiner has argued that certain benefits might be achieved
by use of the Applicant's invention (e.g., power saving) and
argued that these benefits would have made it obvious to
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modify the opposite teachings of Conley. However, the
Examiner has pointed to no evidence that such benefits would
be recognized by one of ordinary skill,
(App. Br. 10), and that any such suggested modification of Conley would
eliminate any benefits that the Examiner has identified in the reference.
App. Br. 10 n.1.
Appellant specifically contends "Conley fails to teach or suggest a
copyback operation correcting an error bit before the source data is written
to another page to prevent the writing of the source page of data with an
error to another page." App. Br. 11. Appellant further asserts the Examiner
agrees that Conley "fails to teach programming of the read data
simultaneously with the transfer and verification of the read data rather than
curing an error bit embedded in the source data before the source data is
written to another page" (App. Br. 11-12), but that the Examiner considers
this distinction to be obvious, without offering any evidence in support of
the finding. App. Br. 12. From this assertion, Appellant argues the
Examiner has failed to make a prima facie case of obviousness due to the
reliance upon improper hindsight reconstruction of the claimed invention.
App. Br. 12.
Here, we see the hindsight question before us as a balancing test, i.e.,
whether the Examiner's proffered combination of references is merely: ( 1)
"the predictable use of prior art elements according to their established
functions" (KSR Int'! Co. v. Teleflex, Inc., 550 U.S. 398, 417 (2007)),
consistent with common sense; or, (2) would an artisan reasonably have
combined the cited references in the manner proffered by the Examiner but
for having the benefit of the claim to use as a guide (i.e., impermissible
hindsight)?
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After reviewing the respective teachings and suggestions of the cited
reference, we find the evidence more strongly supports the first prong of the
balancing test. It is our view that it would have been obvious to an artisan
having general knowledge of memory systems to modify the improved flash
EEPROM memory-based storage subsystem of Conley as stated by the
Examiner. Ans. 4--8. We find the Examiner provided sufficient articulated
reasoning with some rational underpinning to support the legal conclusion of
obviousness. In particular we agree with the Examiner,
The decision of whether to write the data simultaneously while
checking for errors or to wait for the error checking results
before writing the data is an obvious matter of design choice,
with the tradeoff being power saved vs. operation speed.
Conley does not explicitly mention what his device does when
it detects an error but it would have been obvious to one of
ordinary skill in the art at the time the invention was made to
replace the erroneous data with the corrected data, and he
explicitly teaches that it is desirable to "ensure that the data
would be correctly programmed in the new location" (column
3, lines 21-23), the clear implication being that whenever
erroneous data is detected, it is corrected by rewriting the
erroneous data in the flash memory with the corrected data.
Final Act. 7.
As the Supreme Court has held, when there is a design need or market
pressure to solve a problem and there are a finite number of identified,
predictable solutions, a person of ordinary skill has good reason to pursue
the known options within his or her technical grasp. If this leads to the
anticipated success, it is likely the product not of innovation but of ordinary
skill and common sense. In that instance the fact that a combination was
obvious to try might show that it was obvious under§ 103. KSR, 550 U.S.
at 421.
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Moreover, we are of the view that modifying Conley's teachings
regarding the copyback and checking of flash memory data would have been
obvious to try since there are only three possible options, with each option
having a predictable result, as outlined by the Examiner (Ans. 4--5):
1. Read the data from the flash memory, copy it back to the
flash memory, and then check for errors in the data just copied.
If errors are found, write the corrected data to the flash
memory.
2. Read the data from the flash memory, check for errors
and correct them, and then copy it back to the flash memory.
3. Read the data from the flash memory and copy it back to
the flash memory while checking for errors. If errors are found,
write the corrected data to the flash memory.
These are the only three possibilities for performing error
checking and correction (ECC) with a copyback operation.
Either the ECC happens after, before, or while the data is
copied back. There are no other options. Each option has
advantages and disadvantages, and they relate to time
consumed, po\~1er consumed, complexity, etc.
Ans. 5.
The Examiner finds the second option listed above is Appellant's
claimed invention, "namely correcting the errors before copying back to the
flash so that only good data is ever written in the flash. This option saves
power since no double writes are ever necessary: erroneous data is corrected
before it is written back to the flash." Ans. 5. The Examiner further finds:
The skilled artisan would be motivated to modify Conley to
perform the ECC before the copyback to save power since if the
ECC is done before the copyback, then each piece of data is
only written once, saving the power required by Conley's
device when it has to write data twice (once when it is
erroneous, then again when it has been corrected by the ECC).
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So since there are just three options, the skilled artisan
would easily weigh all three and determine which was the best
for his/her design requirements.
Ans. 6. We agree with the Examiner's findings that the choice and timing of
error-correction techniques would have been an obvious design choice, well
within the capability of a skilled artisan.
We agree because Appellant has not demonstrated that the Examiner's
proffered modification of Conley would have been "uniquely challenging or
difficult for one of ordinary skill in the art." See Leapfrog Enters., Inc. v.
Fisher-Price, Inc., 485 F.3d 1157, 1162 (Fed. Cir. 2007) (citing KSR, 550
U.S. at 418). Nor has Appellant provided objective evidence of secondary
considerations which our reviewing court guides "operates as a beneficial
check on hindsight." Cheese Sys., Inc. v. Tetra Pak Cheese and Powder
Sys., 725 F.3d 1341, 1352 (Fed. Cir. 2013).
Issue 3(a)
Appellant further argues "Conley fails to teach a page buffer" (App.
Br. 16), but
there is no teaching that the master and slave data registers (nor
any registers in Conley) are a "page buffer" as required by the
pending claims of this application. Fig. 6 ... [of Conley], (as
well as its corresponding description) does not provide any
guidance as to whether the slave and master data registers are a
"page buffer."
App. Br. 16.
The Examiner finds, and we agree:
Conley does not use the term "page buffer" but his device
clearly includes circuitry to sense and latch the pages of data
going into and coming out of his flash memories, so it can be
fairly said that his device includes a page buffer. Appellant's
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claims characterize the page buffer as comprising sensing and
latching units and Conley's device certainly includes sensing
and latching units as mentioned above, so Appellant's
arguments are not persuasive. Conley's device senses and
latches pages and therefore can be said to buff er pages and
therefore can be said to contain a page buffer.
Ans. 8-9. 6 We note Appellant does not point to any evidence of record that
would demonstrate the Examiner's interpretation is overly broad,
unreasonable, or inconsistent with Appellant's Specification.
Therefore, based upon the findings above, on this record, we are not
persuaded of error in the Examiner's reliance on the teachings and
suggestions of the cited prior art to teach or suggest the disputed limitation
of claim 10, nor do we find error in the Examiner's resulting legal conclusion
of obviousness. Therefore, we sustain the Examiner's obviousness rejection
of independent claim 10, and grouped claims 11-31and37-39 which fall
therewith. See Claim Grouping, supra.
REPLY BRIEF
To the extent Appellant may advance new arguments in the Reply
Brief (Reply Br. 4--7) not in response to a shift in the Examiner's position in
the Answer, we note arguments raised in a Reply Briefthat were not raised
6 Any special meaning assigned to a term "must be sufficiently clear in the
specification that any departure from common usage would be so understood
by a person of experience in the field of the invention." Multiform
Desiccants, Inc. v. Medzam, Ltd., 133 F.3d 1473, 1477 (Fed. Cir. 1998); see
also Helmsderfer v. Bobrick Washroom Equip., Inc., 527 F.3d 1379, 1381
(Fed. Cir. 2008) ("A patentee may act as its own lexicographer and assign to
a term a unique definition that is different from its ordinary and customary
meaning; however, a patentee must clearly express that intent in the written
description.").
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in the Appeal Brief or are not responsive to arguments raised in the
Examiner's Answer will not be considered except for good cause (see
37 C.F.R. § 4I.4I(b)(2)), which Appellant has not shown.
CONCLUSIONS
(1) The OTDP Rejections RI and R2 of claims I 0-39 have been
rendered moot by the filing and entry of a Terminal Disclaimer. Therefore,
OTDP rejections RI and R2 are no longer before us on appeal.
(2) The Examiner did not err with respect to obviousness Rejection
R3 of claims I0-3 I and 37-39 under 35 U.S.C. § I03(a) over the cited prior
art of record, and we sustain the rejection.
DECISION
We dismiss as moot the obviousness-type double patenting rejections
of claims I0-39.
We affirm the Examiner's decision rejecting claims 10-31 and 37-39
under 35 U.S.C. § I03.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § I. I36(a)(l )(iv).
AFFIRMED
I2