Ex Parte Lee

Board of Patent Appeals and Interferences

Feb 9, 2011

10390667 (B.P.A.I. Feb. 9, 2011)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte JINAEON LEE
____________

Appeal 2009-007769
Application 10/390,667
Technology Center 2100
____________

Before JAY P. LUCAS, JOHN A. JEFFERY, and
CAROLYN D. THOMAS, Administrative Patent Judges.

JEFFERY, Administrative Patent Judge.

DECISION ON APPEAL1
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 1-6 and 8-35. We have jurisdiction under 35 U.S.C.
§ 6(b). We affirm-in-part.

1 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, or for filing a request for rehearing,
as recited in 37 C.F.R. § 41.52, begins to run from the “MAIL DATE”
(paper delivery mode) or the “NOTIFICATION DATE” (electronic delivery
mode) shown on the PTOL-90A cover letter attached to this decision.
Appeal 2009-007769
Application 10/390,667

2
STATEMENT OF THE CASE
Appellant invented a flash file system that interfaces flash memory
and a host system. See generally Spec. ¶ 0008. Claim 1 is reproduced
below:
1. A flash file system, comprising:
a flash memory; and
a subsystem interfacing between the flash memory and a
host system, the subsystem including,
a host system interface interfacing with the host system;
a cache memory system, the cache memory system
having a storage capacity of a number of data units, and storing
data for transfer to and from the host system via the host system
interface based on a logical addresses received from the host
system via the host system interface, the data being stored in
association with the logical addresses;
a flash translation layer unit mapping a logical address
received from the cache memory into a physical address of the
flash memory; and
a flash memory interface interfacing with the flash
memory to transfer data to the flash memory from the cache
memory system based on the physical address received from
the flash translation layer unit and to transfer data from the
flash memory to the cache memory system based on the
physical address received from the flash translation layer unit.

The Examiner relies on the following as evidence of unpatentability:
Tobita US 6,275,436 B1 Aug. 14, 2001
Tamura US 2003/0033573 A1 Feb. 13, 2003

Appeal 2009-007769
Application 10/390,667

3
THE REJECTION
The Examiner rejected claims 1-6 and 8-35 under 35 U.S.C. § 103(a)
as unpatentable over Tobita and Tamura. Ans. 3-16.2

THE CONTENTIONS
Claims 1-6, 7-17, and 25-33
Regarding independent claim 1, the Examiner finds that Tobita
discloses all recited limitations, except for the cache memory storing data for
transfer to and from the host system through the host system interface based
on a logical address received from the host system. Ans. 3-5. The Examiner
relies on Tamura to cure the deficiency and to provide a reason for
combining the references. Ans. 5.
Appellant argues, among other things, that (1) neither Tobita nor
Tamura teaches a cache memory storing data for transfer to and from the
host system based on and in association with logical addresses, and (2) the
Examiner failed to provide a proper reason to combine the references’
teachings. App. Br. 14-26; Reply Br. 1-14.
The issue before us, then, is as follows:

ISSUE
(1) Under § 103, has the Examiner erred in rejecting claim 1 by
finding that Tobita and Tamura collectively would have taught or suggested

2 Throughout this opinion, we refer to (1) the Appeal Brief filed June 9,
2008; (2) the Examiner’s Answer mailed September 8, 2008; and (3) the
Reply Brief filed November 10, 2008.
Appeal 2009-007769
Application 10/390,667

4
a cache memory system that stores data to and from the host system based
on and in association with logical addresses?
(2) Is the Examiner’s reason to combine the teachings of these
references supported by articulated reasoning with some rational
underpinning to justify the Examiner’s obviousness conclusion?

FINDINGS OF FACT (FF)
1. Appellant’s buffer RAM 44 stores data received from flash
memory interface 28 at step S912 in the buffer RAM 44 of the pseudo RAM
24. The buffer 44 then sends the data to host 2. See Spec. ¶¶ 0037-39; Figs.
2, 3, 6.
2. Tobita discloses a flash memory system having a flash memory
2001, a bus 2002 for an information apparatus used by a host, an interface
circuit 2003, a controller 2004, an address translation table 2005, a write
buffer 2006, a DMA controller (DMAC) 2007, an interrupt information
register 2008, and connections (shown by arrows). Tobita, col. 31, ll. 31-63;
Fig. 50.
3. Tobita states that the host sends an access request through host
bus 2002 when storing or reading file data. When the file data is stored, the
host specifies the logical address to store the data and transfers the data. The
controller 2004 writes the logical address specified by the host and the
physical address of the write buffer in which the data is to be stored into the
translation table 2005. The controller 2004 also starts the DMAC 2007 to
store the data in the write buffer 2006, and the controller transfers the data
from the write buffer to the flash memory 2001. Tobita, col. 32, ll. 5-8,
18-21, 29-31, 48-49; col. 33, l. 44 – col. 34, l. 4; Figs. 50, 53.
Appeal 2009-007769
Application 10/390,667

5
4. When file is read, Tobita’s host specifies the logical address and
requests the file data stored “here” should be transferred. Specifically, the
controller 2004 references the translation table 2005 from the logical address
specified by the host to find where the data is physically stored, and the
DMAC 2007 then transfers the data to the host bus 2002. Tobita, col. 32, ll.
8-10, 33-39, 48-49; col. 33, ll. 31-43; Figs. 50, 52.
5. Tobita’s file data storage location may be the flash memory or the
write buffer. Tobita, col. 32, ll. 40-45.

ANALYSIS
We begin by construing the limitation of claim 1 which calls for, in
pertinent part, “a cache memory system . . . storing data for transfer to and
from the host system . . . based on [] logical addresses received from the host
system and . . . in association with the logical addresses.” Thus, the recited
cache memory system must store data for transfer both to and from the host
system. To illustrate, Appellant’s Figure 6 provides an example of how the
buffer 44 (e.g., cache memory) stores data at step S912 in the buffer RAM
44 of the pseudo RAM 24 from the flash memory interface 28 and then
sends data to host 2. See FF 1. Thus, when giving the claimed cache
memory system its broadest reasonable construction in light of the
disclosure, the claimed cache memory system must store data for transfer
both from the host system and to the host system. See In re Am. Acad. of
Sci. Tech Ctr., 367 F.3d 1359, 1364 (Fed. Cir. 2004) (internal citations and
quotations omitted).

Appeal 2009-007769
Application 10/390,667

6
Tobita discloses an embodiment with a flash file system in Figure 50.
FF 2. This system includes flash memory (e.g., 2001), a host system (e.g.,
2002), and a “subsystem” (e.g., 2003-08). Id. The “subsystem” includes a
write buffer 2006 (i.e., memory). See id. As a memory element, Tobita’s
write buffer temporarily stores data transferred from the host, and, in that
sense, caches data. See FF 3. But the write buffer does not store data
transferred to the host (see FF 4)—a crucial requirement of the recited cache
memory system. In this regard, the host sends an access request to read file
data or transfer data to the host system. Id. Although Tobita’s controller
references a table to find where the data is stored (see id.), Tobita does not
indicate where the file data is stored during this read operation. Tobita does
state that the file data storage location may be the flash memory or the write
buffer. FF 5. But this data storage in the write buffer apparently refers to
write—not read—operations. Indeed, this conclusion is bolstered by the
very label “write buffer” which indicates that the buffer writes data (i.e.,
transfers data from the host to the buffer), but does not read data (i.e.,
transfers data from the buffer (“cache memory system”) to the host as
required by claim 1.
Additionally, the Examiner has mapped the cache memory in Figures
49, 82, 87, and 101 to the recited cache memory system that stores data for
transfer to the host system. See Ans. 3-4. But as Appellant correctly
indicates (App. Br. 20-21), Figures 49, 82, 87, and 101 describe a different
embodiment from the Figure 50 embodiment relied on for other elements of
the claim. Compare Tobita, col. 15, ll. 65-67; col. 17, ll. 17-19; col. 18, ll.
Appeal 2009-007769
Application 10/390,667

7
3-5 (describing Figures 49, 82, 97, and 101 as a fourth3 embodiment) with
col. 16, ll. 1-2 (describing Figure 50 as a second embodiment). Thus, while
we agree with the Examiner that a reference must be considered as a whole,
the Examiner must nonetheless provide a reason for combining the fourth
embodiment’s cache memory with the second embodiment shown in Figure
50. See KSR Int’l Co. vs. Teleflex Inc., 550 U.S. 398, 418 (2007) (internal
citations omitted). The Examiner, however, has not articulated any rationale
to combine these disparate teachings, let alone articulate the requisite
rational underpinning to support a conclusion for obviousness regarding
these diverse embodiments.
Lastly, the Examiner has not relied upon Tamura to cure the
deficiency of a buffer or cache memory system that stores data for transfer to
and from the host system as recited in claim 1. Nor will we engage in such
an inquiry in this regard here in the first instance on appeal.
For the foregoing reasons, Appellant has persuaded us of error in the
obviousness rejection of: (1) independent claim 1; (2) independent claims
14, 25, and 32, which recite commensurate limitations; and (3) dependent
claims 2-6, 8-13, 15-17, 26-31, and 33 for similar reasons.

Claims 18-20, 34, and 35
The scope of independent claim 18 differs from claim 1. Specifically,
claim 18 does not recite a cache memory, but claims the details of the flash

3 Some of the figures are described as the “forth” embodiment. We presume
this a typographical error, and Tobita’s disclosure intended to state “fourth”
embodiment.
Appeal 2009-007769
Application 10/390,667

8
translation layer unit storing a physical address table and a logical address
table indicating whether a portion of flash memory is erased.
The Examiner relies on the discussion for claim 1 to meet the
limitations of claim 18. See Ans. 10. Additionally, the Examiner maps the
recited physical address table and logical address table to Tobita’s address
translation table 2005, the logical sector table 1095, and the physical sector
table 1105.4 See Ans. 10-11.
Appellant refers to the arguments made with respect to claim 1.
Among other assertions, Appellant also argues that (1) Tobita’s Figure 50
embodiment only has one translation table, and (2) the Examiner has mixed
embodiments. App. Br. 30-35.
The issue before us, then, is as follows:

ISSUE
Under § 103, has the Examiner erred in rejecting claim 18 by finding
that Tobita and Tamura collectively would have taught or suggested a flash
translation layer storing a logical address table that indicates for each
physical address whether a portion of the flash memory is erased?

ADDITIONAL FINDINGS OF FACT
6. Tobita discloses another flash memory system that has a control
table consisting of five tables, including: a physical address table 1105, a

4 Tobita describes a physical sector table “1005” (see Tobita, col. 23, l. 42),
but Figure 27 shows the physical sector table as 1105. As other elements
(e.g., garbage buffer 1005 in Fig. 1) are also shown using reference character
“1005,” we presume the description of the physical sector table as “1005” is
a typographical error.
Appeal 2009-007769
Application 10/390,667

9
PSRAM logical sector table 1095, and an erasure management table 1108.
Tobita, col. 15, ll. 3-6; col. 22, ll. 17-24; col. 23, ll. 19, 33-44, col. 24, ll.
23-30; Figs. 18, 20, 23, 26, 27.
7. Tobita describes erasing a block’s content. Tobita, col. 1, ll. 61-
63.

ANALYSIS
Based on the evidence before us, we find error in the Examiner’s
rejection of claim 18. We agree with Appellant that the second embodiment
disclosed by Tobita only includes one table (e.g., translation table 2005) and
thus cannot include the recited physical address table and logical address
table. See FF 2. Furthermore, similar to the above discussion, the Examiner
has not established a case of obviousness or articulated a reason to combine
this Figure 50 embodiment with another disclosed embodiment in Tobita,
such as the Figures 20 and 23 embodiment.
Nonetheless, the Examiner also refers to an alternative embodiment
that discloses both a physical address table (e.g., 1105) and a logical sector
table (e.g., 1095). See FF 6. Citing to Tobita’s column one, lines sixty-one
through sixty-three, column twenty-two, lines seventeen through twenty-
two, and Figures 20-23, the Examiner finds Tobita discloses the logical
sector table (e.g., 1095) indicates, for each physical address, whether this
portion of flash memory is erased. See Ans. 11. Figures 20 and 23 do show
an erasure management table 1108. FF 6. However, this table 1108 is
separate from the logical address table 1095 (see id.), and the Examiner has
not provided a reason to combine the tables into the recited logical address
table. See Ans. 10-11. Additionally, Tobita’s erasure management table
Appeal 2009-007769
Application 10/390,667

10
1108 fails to indicate an associated logical address for each physical address
and whether the physical address and logical address association is valid as
required by the logical address table recited in claim 18. Furthermore,
reference to erasing a block’s content (see FF 7; Ans. 11) does not teach a
logical address table indicating, for each physical address, whether the
portion of the flash memory is erased.
For the foregoing reasons, Appellant has persuaded us of error in the
obviousness rejection of: (1) independent claim 18; (2) independent claim
34, which recites commensurate limitations; and (3) dependent claims 19,
20, and 35 for similar reasons.

Claims 21-24
The scope of independent claim 21 differs from both claims 1 and 18.
Like claim 18, claim 21 does not recite a cache memory. Claim 21 only
claims a subsystem configured to store a data entry, and the data entry is
stored in the subsystem for transfer to and from the host system based on the
logical address and in association with the logical address.
The Examiner relies on the discussion for claim 1 to meet the
limitations of claim 21. See Ans. 11. Additionally, the Examiner discusses
other portions of Tobita to meet the recitation of the data entry
corresponding to a file transfer unit and having the same size as the file
transfer unit. See Ans. 11-12.
Appellant argues: (1) Tobita is silent about how the data is stored in
the write buffer; (2) Tobita translates the received logical address into a
physical address and stores the data in association with the physical address;
and (3) Tamura also stores data in the data buffer using the physical sector
Appeal 2009-007769
Application 10/390,667

11
addresses of the flash memory and thus in association with a physical – not
logical – address. App. Br. 36-39.
The issue before us, then, is as follows:

ISSUE
Under § 103, has the Examiner erred in rejecting claim 21 by finding
that Tobita and Tamura collectively would have taught or suggested a flash
file system having subsystem interfacing between the flash memory and a
host system, the subsystem configured to store data entry data for transfer to
and from the host system based on and in association with the logical
address?

ADDITIONAL FINDINGS OF FACT
8. Tobita discloses a translation table 2005, including each write
buffer memory’s block number corresponding to a logical address and a
flash memory/physical sector number. Tobita’s Figure 60 is reproduced
below:
Appeal 2009-007769
Application 10/390,667

12

Figure 60 depicting the translation table
Tobita, col. 31, ll. 56-63; Fig. 60.

ANALYSIS
Based on the evidence before us, we find no error in the Examiner’s
rejection of claim 21. As stated above, claim 21’s scope differs from claim
1, in that the subsystem — and not specifically the cache memory system —
is configured to store data entry data for transfer to and from the host system
based on and in association with the logical address. Thus, Tobita need not
teach the data is stored in a cache memory system during a read operation or
when transferring data to the host system to meet the limitations of claim 21.
In rejecting claim 21, the Examiner references portions of Tobita
discussing the Figure 50 embodiment. See Ans. 12. This flash file system
that includes a host system (e.g., host bus 2002 connects to host) and a flash
Appeal 2009-007769
Application 10/390,667

13
memory 2001. See FF 2. Additionally, between the host system and flash
memory, Tobita has a subsystem that includes interface circuit 2003,
controller 2004, address translation table 2005, write buffer 2006, DMAC
2007, register 2008, and the respective conduits (shown by arrows) that
interconnects these components. See id.
When data is either written to the subsystem’s buffer (e.g., 2004) or
read from the flash memory (e.g., 2001) to be sent to the host (e.g., through
bus 2002), the data must be transferred through Tobita’s above-explained
subsystem. See FF 3-4. Specifically, when data is written or transferred
from the host, the data is stored in the write buffer 2004 (see FF 3), and
when data is read or transferred to the host, the data is stored, at least
temporarily, in the subsystem’s interconnections and interface circuit 2003
(see FF 4). We therefore find that Tobita discloses a subsystem that is
configured to store data entry data for transfer to and from the host system as
recited in claim 21.
Claim 21 also requires “the data entry is stored in the subsystem . . .
based on the logical address; and . . . in association with the logical address.”
Notably, this limitation does not require the data entry to be stored in a
logical address, but rather that the data entry is stored based on and in
association with the logical address. Tobita therefore need only teach the
data entry is stored in the subsystem using a logical address, regardless of
whether the data entry is actually stored in a logical or physical address.
Moreover, even if the data is stored in association with a physical address, as
Appellant asserts (App. Br. 37-38), data can also be stored based on and in
association with the logical address.
Appeal 2009-007769
Application 10/390,667

14
Tobita teaches that, during a write operation, the host specifies a
logical address to store the data. See FF 3. In turn, the controller (e.g.,
2004) writes the logical address specified by the host as well as the write
buffer’s physical address where data is to be stored in a translation table
(e.g., 2005), and a controller stores the data in the write buffer (e.g., 2006)
based on the translation table. See id. Moreover, the translation table 2005
relates this logical address to a write buffer’s memory block number and a
physical address in flash memory. See FF 8. Thus, whenever data is stored
within the subsystem’s write buffer or transferred from the host, the logical
address is used and becomes affiliated with other storage information (e.g.,
the physical address, the write buffer’s memory), demonstrating the data
entry is stored based on and in association with the logical address. See FF
3, 8. Thus, contrary to Appellant’s arguments (App. Br. 37), Tobita is not
entirely silent about how the data is stored in the write buffer.
Similarly, during a read operation, the host specifies a logical address
for the data, and subsystem’s controller (e.g., 2004) refers to the translation
table using the logical address to determine where the data is stored before
transferring data to the host. See FF 4, 8. Moreover, Tobita teaches during
this operation that the logical address is used to obtain the data and, thus, the
data is stored for transfer to the host system based on the logical address.
Moreover, even assuming in this situation that the data is stored in flash
memory, the data will be transferred through Tobita’s above-explained
subsystem, at least temporarily. We therefore find that Tobita teaches,
during both read and write operations, data stored in a subsystem can be
transferred to and from the host system by using the logical address (see FF
Appeal 2009-007769
Application 10/390,667

15
3, 4, 8) or is based on and in association with the logical address as recited in
claim 21.
Finally, we need not address whether Tamura cures the alleged
deficiency (App. Br. 38-39) since Tobita teaches the disputed limitations.
For the foregoing reasons, Appellant has not persuaded us of error in
the obviousness rejection of: independent claim 21 and claims 22-24 not
separately argued with particularity (App. Br. 35-39).

CONCLUSION
Under § 103, the Examiner did not err in rejecting claims 21-24, but
erred in rejecting claims 1-6, 8-20, and 25-35.

ORDER
The Examiner’s decision rejecting claims 1-6 and 8-35 is affirmed-in-
part.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED-IN-PART

pgc

HARNESS, DICKEY & PIERCE, P.L.C.
P.O. BOX 8910
RESTON, VA 20195