Ex Parte LEE

Patent Trial and Appeal Board

Sep 4, 2018

14567595 (P.T.A.B. Sep. 4, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO.
14/567,595
90228 7590
IP & T GROUP LLP
8230 Leesburg Pike
Suite 650
FILING DATE
12/11/2014
09/04/2018
VIENNA, VA 22182
FIRST NAMED INVENTOR
Kang-Seo! LEE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
Pl4H0113/US 4670
EXAMINER
WADDY JR, EDWARD
ART UNIT PAPER NUMBER
2135
MAIL DATE DELIVERY MODE
09/04/2018 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte KANG-SEOL LEE
Appeal2018-002384
Application 14/567,595
Technology Center 2100
Before ALLEN R. MacDONALD, BRUCE R. WINSOR, and
JON M. JURGOV AN, Administrative Patent Judges.
MacDONALD, Administrative Patent Judge.
DECISION ON APPEAL 1
STATEMENT OF CASE
Appellant appeals under 35 U.S.C. § 134(a) from a final rejection of
claims 1-20. We have jurisdiction under 35 U.S.C. § 6(b ).
We AFFIRM.
1 Appellant indicates the real party in interest is SK Hynix Inc. App. Br. 3.
Appeal2018-002384
Application 14/567,595
Illustrative Claims
Illustrative claims 1 and 19 under appeal read as follows ( emphasis,
formatting, and bracketed material added):
1. A semiconductor device comprising:
[A.] one or more internal circuits;
[B.] a nonvolatile memory circuit having a first region suitable for
storing first data for an operation of the nonvolatile memory
circuit and a second region suitable for storing second data for
an operation of the internal circuits;
[ C.] a first register suitable for temporarily storing the first data
used for the operation of the nonvolatile memory circuit;
[D.] one or more second registers suitable for temporarily storing the
second data; and
[E.] a control circuit suitable for controlling the nonvolatile memory
circuit to transmit the first data and the second data to the first
register and the second registers, respectively, when a boot-up
operation is performed.
19. A method of operating a semiconductor device with a nonvolatile
memory circuit, the method comprising:
[A.] activating a boot-up signal;
[B.] performing a first boot-up operation on a first nonvolatile
memory region of the nonvolatile memory circuit based on the
boot-up signal;
[C.] optimizing the nonvolatile memory circuit based on data obtained
by the first boot-up operation; and
[D.] performing a second boot-up operation on a second nonvolatile
memory region of the nonvolatile memory circuit based on the
boot-up signal after the nonvolatile memory circuit is
optimized.
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Application 14/567,595
Rejections
A.
The Examiner rejected claims 1, 2, 5-13, and 15-18 under 35 U.S.C.
§ 103 as being unpatentable over the combination of Tokiwa (US
2007/0147144 Al; pub. June 28, 2007), Best et al. (US 2010/0091537 Al;
pub. Apr. 15, 2010), and Glover (US 5,987,562; iss. Nov. 16, 1999). Final
Act. 5-28.
Appellant presents arguments for claim 1. Appellant does not present
separate arguments for claims 2, 5-13, and 15-18. Except for our ultimate
decision, we do not address claims 2, 5-13, and 15-18 further herein.
B.
The Examiner rejects claims 3, 4, and 14 under 35 U.S.C. § I03(a) as
being unpatentable over the combination of Tokiwa, Best, Glover, and
Garnett (US 2003/0229814 Al; pub. Dec. 11, 2003). Final Act. 28-30.
Appellant argues claims 3, 4, and 14 by reference to the arguments
for claim 1. Thus, the rejection of these claims turns on our decision as to
claim 1. Except for our ultimate decision, we do not discuss the § 103
rejection of claims 3, 4, and 14 further herein.
C.
The Examiner rejects claims 19 and 20 under 35 U.S.C. § I03(a) as
being unpatentable over the combination of Tokiwa, Best, Glover, and
Kirshenbaum et al. (US 2008/0082812 Al; pub. Apr. 3, 2008). Final Act.
30-33.
Appellant presents arguments for claim 19. Appellant does not
present separate arguments for claim 20. Except for our ultimate decision,
we do not address claim 20 further herein.
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Appeal2018-002384
Application 14/567,595
Issues on Appeal
Did the Examiner err in rejecting claims 1 and 19 as being obvious?
ANALYSIS
We have reviewed the Examiner's rejections in light of Appellant's
arguments (Appeal Brief and Reply Brief) that the Examiner has erred. We
disagree with Appellant. Except as noted below, we adopt as our own
(1) the findings and reasons set forth by the Examiner in the action from
which this appeal is taken and (2) the reasons set forth by the Examiner in
the Examiner's Answer in response to Appellant's Appeal Brief. We concur
with the conclusions reached by the Examiner. We highlight the following
points.
A.
Appellant raises the following argument in contending that the
Examiner erred in rejecting claim 1 under 35 U.S.C. § 103(a).
Glover fails to teach a first register suitable for temporarily
storing first data used for an operation of a nonvolatile memory
circuit, as recited in claim 1.
More specifically, the Office Action at pages 11-12 asserts
that, in Fig. 1 of Glover, Glover teaches the features related to
the first register of claim 1.
App. Br. 8.
Referring to Fig. 1 of Glover, it appears that Glover merely
discloses that the operational parameters stored in the ROM 29
are provided to the parameter memory 22 during start-up, and are
accessed by the various circuit modules of read channel 18 for
use during read operations. That is, the operational parameters of
Glover corresponds to second data for an operation of internal
circuits (i.e., a disk/head assembly 12 and the read channel 18).
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Appeal2018-002384
Application 14/567,595
However, the ROM 29 of Glover does not disclose temporarily
storing first data used/or an operation of a nonvolatile memory
circuit (i.e., the ROM 29 itself).
App. Br. 9--10 (emphasis omitted).
The Examiner presents the following response to Appellant's above
arguments.
Best teaches a register for temporarily storing the data as cited
in the 12 January 2017 Office Action ... [para. 0072, first and
second sentence]. Glover is applied to teach a first register for
storing first data [ operational parameters] used for the operation
of the nonvolatile memory circuit [ operation of disk drive mass
storage system 30] as cited in the 12 January 2017 Office Action
["In operation, disk drive mass storage system 30 goes through
an initialization or start-up routine when power is initially
provided. One such routine instructs microprocessor 2 8 to
supply operational parameters, previously stored in ROM 29, to
parameter memory 22 of SSD channel 10 through data/parameter
path 13. The operational parameters are then stored in memory
registers of parameter memory 22 for use by read channel 18
during read operations. The operational parameters have been
previously calculated, normally during bum-in, and stored in
ROM 29. The operational parameters adapt or optimize the
circuitry of read channel 18 to the specific physical and
magnetic characteristics of disk drive mass storage system 30.]
Ans. 34 (Examiner's emphasis omitted; Panel emphasis added).
We are not persuaded by Appellant's argument. First, as to
Appellant's "register for temporarily storing" argument, Appellant does not
address the actual reasoning of the Examiner's rejection. Instead, Appellant
attacks the Glover reference singly for lacking a teaching that the Examiner
relied on a combination of references to show. It is well-established that one
cannot show non-obviousness by attacking references individually where the
rejections are based on combinations of references. See In re Keller, 642
F.2d 413,426 (CCPA 1981); In re Merck & Co., Inc., 800 F.2d 1091, 1097
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Appeal2018-002384
Application 14/567,595
(Fed. Cir. 1986). References must be read, not in isolation, but for what they
fairly teach in combination with the prior art as a whole. Merck, 800 F .2d at
1097.
Second, as to Appellant's "operation of the nonvolatile memory
circuit" argument, we agree with the Examiner that the disk drive mass
storage system 30 of Glover is a nonvolatile memory circuit. Although the
Examiner does not rely on Appellant's admitted prior art and we do not in
reaching our decision, we do note that Appellant admits the prior art
includes the now argued "a first register suitable for temporarily storing first
data used for an operation of a nonvolatile memory circuit."
The setting circuit 420 may set various setting values
required for operation of the memory device, using the setting
information stored in the register 41 O_ 4. For example, the setting
circuit 420 may set an internal voltage level and various
latencies. The information stored in the registers 41 O_O to 41 O_ 4
is maintained only while power is supplied.
Spec. ,r 26 (describing Fig. 4 (prior art)).
B.
Appellant raises the following argument in contending that the
Examiner erred in rejecting claim 19 under 35 U.S.C. § 103(a).
Glover fails to teach optimizing a nonvolatile memory
circuit based on data obtained by a first boot-up operation, as
recited in claim 19.
More specifically, the Office Action at page 31 asserts that
Glover teaches the features related to the optimizing of the
nonvolatile memory circuit recited in claim 19.
App. Br. 12.
[I]t appears that Glover merely discloses that the operational
parameters optimizes internal circuits (i.e., a disk/head assembly
12 and the read channel 18), not a nonvolatile memory circuit
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Appeal2018-002384
Application 14/567,595
(i.e., the ROM 29) storing the operational parameters itself.
However, Glover does not disclose how to optimize a nonvolatile
memory circuit based on data obtained by a first boot-up
operation.
App. Br. 12-13 ( emphasis omitted).
The Examiner presents the following response to Appellant's above
arguments.
Glover teaches optlm1zmg [ operational parameters adapt or
optimize the circuitry of read channel 18 to the specific physical
and magnetic characteristics of disk drive mass storage system
30] the nonvolatile memory circuit [ operation of disk drive mass
storage system 30] based on data obtained be the first boot-up
operation as cited in the 12 January 2017 Office Action.
Ans. 37 (Examiner's emphasis omitted; Panel emphasis added).
We are not persuaded by Appellant's argument. Again, we agree with
the Examiner that the disk drive mass storage system 30 of Glover is a
nonvolatile memory circuit as claimed.
C.
Although not timely filed, we exercise our discretion and review the
rejection based on the following untimely argument. Appellant also raises
the following argument in contending that the Examiner erred in rejecting
claim 19 under 35 U.S.C. § 103(a).
According to claim 19, a first boot-up operation of the
nonvolatile memory is performed and the nonvolatile memory is
optimized by data obtained in the first boot-up. Furthermore, a
second boot-up operation of the nonvolatile memory is
performed after the nonvolatile memory is optimized. That is,
according to claim 19, (1) first boot-up operation of the NVM ->
(2) optimizing of the NVM by data of the first boot-up->
(3) second boot-up operation of the NVM are performed
sequentially. However, [] Tokiwa, Glover and Best fail to teach
[the] above features of claim 19.
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Appeal2018-002384
Application 14/567,595
Reply Br. 4--5.
We are not persuaded by Appellant's argument. Again, Appellant
does not address the actual reasoning of the Examiner's rejection. Instead,
Appellant attacks the Tokiwa, Glover, and Best references for lacking a
teaching that the Examiner relied on a combination of references including
Kirshenbaum to show. Appellant does not dispute the Examiner's finding
that Kirshenbaum teaches this argued limitation of claim 19. Final Act. 32.
CONCLUSIONS
(1) The Examiner has not erred in rejecting claims 1-20 as being
unpatentable under 35 U.S.C. § 103(a).
(2) Claims 1-20 are not patentable.
DECISION
The Examiner's rejections of claims 1-20 are affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED
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