Ex Parte LeeDownload PDFBoard of Patent Appeals and InterferencesAug 31, 201110423942 (B.P.A.I. Aug. 31, 2011) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 10/423,942 04/28/2003 Dong-Hyun Lee 2557-000134/US 9874 30593 7590 09/01/2011 HARNESS, DICKEY & PIERCE, P.L.C. P.O. BOX 8910 RESTON, VA 20195 EXAMINER ALMO, KHAREEM E ART UNIT PAPER NUMBER 2816 MAIL DATE DELIVERY MODE 09/01/2011 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE BOARD OF PATENT APPEALS AND INTERFERENCES ____________ Ex parte DONG-HYUN LEE ___________ Appeal 2009-014529 Application 10/423,942 Technology Center 2800 ____________ Before MAHSHID D. SAADAT, JASON V. MORGAN, and JULIE K. BROCKETTI, Administrative Patent Judges. BROCKETTI, Administrative Patent Judge. DECISION ON APPEAL Appeal 2009-014529 Application 10/423,942 2 STATEMENT OF THE CASE Introduction Appellant appeals under 35 U.S.C. § 134(a) from a final rejection of claims 26-45. We have jurisdiction under 35 U.S.C. § 6(b). Exemplary Claim(s) Exemplary independent claim 26 under appeal reads as follows: 26. A clock distribution network, comprising: a plurality of clock drivers for outputting clock signals, at least two of the plurality of clock drivers having unequal driving capacities; and a grid distribution network functionally coupled to a chip region for distributing the clock signals output from the plurality of clock drivers, the chip region defined by n sides, where n ≥ 3, the sides intersecting at n vertices, wherein the plurality of clock drivers are arranged along one side of the chip region such that a first clock driver having a first driving capacity C1 is located a first minimum distance D1 from the n vertices and a second clock driver having a second driving capacity C2 is located a second minimum distance D2 from the n vertices, and wherein the expressions D2 > D1 and C2 > C1 are both satisfied, further wherein the driving capacity of each clock driver is proportional to a separation distance D by which each clock driver is separated from the closest one of the n vertices. Appeal 2009-014529 Application 10/423,942 3 Rejections on Appeal1 The Examiner rejected claims 26-32, 39, and 43-45 under 35 U.S.C. § 102(b) as being anticipated by Mitra (US 5,880,607). The Examiner rejected claims 33-38 and 40-42 under 35 U.S.C. § 103(a) as being unpatentable over Mitra in view of Watanabe et al. (US 5,172,330). Appellant’s Contentions (1) Appellant contends that the Examiner erred in rejecting claims 26-30 and 32, because: Mitra at least fails to disclose “[a] clock distribution network, comprising: a plurality of clock drivers …; and a grid distribution network …, the plurality of clock drivers are arranged along one side of the chip region such that a first clock driver having a first driving capacity C1 is located a first minimum distance D1 from the n vertices and a second clock driver having a second driving capacity C2 is located a second minimum distance D2 from the n vertices, and wherein the expressions D2 > D1 and C2 > C1 are both satisfied, further wherein the driving capacity of each clock driver is proportional to a separation distance D by which each clock driver is separated from the closest one of the n vertices,” as recited in independent claim 26. (App. Br. 10-11). [T]here is simply no disclosure in Mitra indicating the driving capacity of the various buffers are proportional to a separation distance from a closest one of n vertices. 1 We note that claims 27 and 42 were cancelled in a prior amendment filed January 23, 2007. Therefore, claims 27 and 42 are not on appeal before this panel. Appeal 2009-014529 Application 10/423,942 4 (App. Br. 15; Reply Br. 4) (emphasis omitted). (2) Appellant contends that the Examiner erred in rejecting claim 31 because: Mitra . . . fails to disclose the features of independent claim 26 and that “the second clock driver is positioned an equal distance from two vertices sharing a common side; and a third clock driver having a third driving capacity C3 is positioned between the second clock driver and the first clock driver, wherein the expression C3 < C2 and C3 < C1 is satisfied,” as recited in dependent claim 31. (App. Br. 16). (3) Appellant contends that the Examiner erred in rejecting claim 39 because: Mitra at least fails to disclose a clock distribution network including “a plurality of clock drivers connected to the grid distribution network and arranged along an edge of the chip region, the clock drivers configured whereby a clock driver having a first driving capacity is positioned between a closest of the two ends and all clock drivers having a higher driving capacity, wherein each clock driver has a driving capacity C that is proportional to a separation distance D between the clock driver and a closest end of the two ends that define an edge of the chip region along which the clock driver is positioned,” as recited in independent claim 39. (App. Br. 17). (4) Appellant contends that the Examiner erred in rejecting claims 43-45 because: Mitra at least fails to [disclose] various features and operations of the method for supplying [a] signal to a semiconductor chip region having a plurality of circuit elements recited in independent claim 43. Appeal 2009-014529 Application 10/423,942 5 (App. Br. 18). (5) Appellant contends that the Examiner erred in rejecting claims 33-38 because: Mitra in combination with Watanabe at least fails to disclose, teach or suggest “a clock distribution network comprising: a plurality of primary clock drivers arranged along each of n edges of the chip region for outputting clock signals, the edges of the chip region intersecting at n corners, n ≥ 3, wherein the plurality of primary clock drivers arranged along each edge of the chip region are arranged such that a selected primary clock driver has a driving capacity that is greater than a driving capacity of any other primary clock driver positioned between the selected primary clock driver and a closest of two corners that define the edge,” as recited in independent claim 33. (App. Br. 19). (6) Appellant contends that the Examiner erred in rejecting claims 40-41 because: Mitra in combination with Watanabe at least fails to disclose, teach or suggest the features of independent claim 39 from which claims 40 and 41 depend. (App. Br. 20). Issues on Appeal Did the Examiner err in rejecting claims 26, 28-41, and 43-45 under 35 U.S.C. § 102(b) and 35 U.S.C. § 103(a) because Mitra fails to disclose the argued claim limitations? Appeal 2009-014529 Application 10/423,942 6 ANALYSIS We agree with Appellant’s contentions and analysis. Our review finds that Mitra fails to disclose the argued claim limitations. CONCLUSIONS (1) Appellant has established that the Examiner erred in rejecting claims 26, 28-32, 39, and 43-45 as being unpatentable under 35 U.S.C. § 102(b) and claims 33-38, 40, and 41 as being unpatentable under 35 U.S.C. § 103(a). (2) On this record, claims 26, 28-41, and 43-45 have not been shown to be unpatentable. DECISION The Examiner’s rejection of claims 26, 28-41, and 43-45 is reversed. REVERSED msc Copy with citationCopy as parenthetical citation