Ex Parte Lea et al

Board of Patent Appeals and Interferences

May 24, 2012

10669247 (B.P.A.I. May. 24, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte PERRY LEA, JUSTEN R. MELTZ, and MICHAEL TANG
____________

Appeal 2009-009292
Application 10/669,247
Technology Center 2600
____________

Before MAHSHID D. SAADAT, MARC S. HOFF and
CARL W. WHITEHEAD, JR., Administrative Patent Judges.

WHITEHEAD, JR., Administrative Patent Judge.

DECISION ON APPEAL
Appeal 2009-009292
Application 10/669,247

2
STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134 from a final rejection of
claims 1-23. Appeal Brief 4. We have jurisdiction under 35 U.S.C. § 6(b)
(2002). We reverse.

Introduction
The invention is an image data processing device and method
designed to process image data in a manner that may reduce wear on mass
storage devices such as hard disks. See generally Specification 4.

Exemplary Claim
Exemplary independent claim 1 under appeal reads as follows:
1. An image forming device comprising:

a scanner configured to scan one or more objects and
generate image data representing each of the one or more
objects;

a memory configured to store each of the image data as a
page of data;

a page frame memory configured to store a page of data,
copied from the memory, that is to be imaged;

an imaging mechanism configured to receive the page of
data from the page frame memory and generate an image from
the page of data onto a print media; and

a dual bus system configured to allow parallel
transmission of data where the image data can be transmitted
from the scanner to the memory simultaneously with
Appeal 2009-009292
Application 10/669,247

3
transmitting the page of data from the page frame memory to
the imaging mechanism.

Rejections on Appeal
Claims 1-4, 6-8, 10-12, 16-20, 22, and 23 stand rejected under
35 U.S.C. 103(a) as being unpatentable over Shishizuka (U.S. Patent
Number 6,697,898 B1; issued February 24, 2004) and Westervelt (U.S.
Patent Application Number 2003/0121330 A1; published December 18,
2003). Answer 3-21.
Claims 5, 9, 13-15, and 21 stand rejected under 35 U.S.C. 103(a) as
being unpatentable over Shishizuka, Westervelt and “well known prior art”.
Answer 21-25.

Issue on Appeal
The dispositive issue is: does the combination of Shishizuka and
Westervelt disclose or suggest the claimed dual bus configuration wherein
one bus is connected to transmit data while another bus allows simultaneous
transmission of a page of data?

ANALYSIS
Appellants argue that:
The Office Action cites the “DoEngine” of Shishizuka as
teaching the claimed dual bus system. Within the DoEngine
(which is best seen in Figure 4), the Office Action cites two
buses, the G bus 404 and the B bus 405. (Office Action, page
5). However, the DoEngine fails to teach the claimed
configuration. The G bus 404 transmits data between the
scanner controller 4302 to the cache memory 403 (via system
App
App

App
eal 2009-0
lication 10
bu
m
br
fr
G
m
sy
Sh
ob
re
eal Brief 1
F

Th
which co
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09292
/669,247
s bridge 4
emory 40
idge 402)
om the cac
bus and B
emory and
stem are
ishizuka.
viousness
versed.
2.
Shishizu
igure 4 dep
e DoEngi
mprises a
r manufac
02), and
3 to the
. A page
he memo
bus conf
the claim
not taught
Shishizu
rejection.
ka’s Figur
icts a bloc
ne is a sin
processor
tured by M
4
the B bus
printer co
frame mem
ry 403) is
iguration.
ed arrang
or sugge
ka fails
The rejec
e 4 is repr
k diagram
gle-chip sc
core comp
IPS Tech
transmits
ntroller 43
ory (bein
not presen
Thus, the
ement with
sted by th
to supp
tion is im
oduced be
of the Do
anning pr
atible wit
nologies,
data from
03 (via
g a separ
t and not
claimed
the recit
e G and
ort a pr
proper and
low:
Engine.
inting eng
h an R400
Inc., a
the cach
system bu
ate elemen
part of th
page fram
ed dual bu
B buses o
ima faci
should b
ine
0
e
s
t
e
e
s
f
e
e

Appeal 2009-009292
Application 10/669,247

5
processor peripheral controller, a memory controller, a
scanner/printer controller, a PCI interface and so on.

Shishizuka, column 6, lines 65 to column 7, lines 2.
The Examiner contends:
SHISHIZUKA cites, “This controller consists of a FIFO which
is a buffer to transfer image data to the printer by way of the
GBI (G bus/B bus I/F) and a circuit which controls the FIFO”;
col. 44, lines 14 - 18. As shown in Fig. 66, the FIFO controller
6603 is a component of the “printer controller” 4303; col. 4,
line 61. As shown in Fig. 4 and Fig. 91, the “printer controller”
4303 is a component of the “DoEngine”.

That is, the printer FIFO is an element that is separate from the
“cache memory 403[sic]”.

In addition, SHISHIZUKA’s “printer FIFO” (i.e., “page frame
memory”) is contained in a printer image data transfer FIFO
controller 6603 which, in turn, is connected to the G & B buses
by means of the GBI (G bus/B bus I/F) interface.
Answer 26.

App
App

throu
Shis
Figu
contr
App
from
26, 2
or th
eal 2009-0
lication 10
Figure
“The pri
gh the vid
hizuka, co
Appellan
re 77 whic
oller 6603
ellants rea
the cache
nd and 3rd
e FIFO 77
09292
/669,247
Shishizu
66 depicts
nter contro
eo I/F to i
lumn 41, l
ts contend
h shows th
which inc
son that th
memory 4
paragraph
01 teach a
ka’s figure
a block di
ller is a bl
nterface w
ines 45-48
that the E
e compon
ludes a PR
e Examine
03 and is
s) is not co
page fram
6
66 is repr
agram of a
ock which
ith the G b
.
xaminer c
ents of a F
INTER F
r’s statem
connected
rrect and c
e memory
oduced be
printer co
is connec
us/B bus
ited sectio
IFO (Firs
IFO 7701
ent that th
to the GB
onclude th
that store
low:
ntroller 43
ted to the
I/F unit.”
ns actuall
t In, First O
. Reply B
is FIFO is
I interface
at the cite
s a page o
03.
printer
See
y refer to
ut) buffe
rief 2.
separate
(EA page
d sections
f data or

r

Appeal 2009-009292
Application 10/669,247

7
that the page of data is copied from the memory as claimed. Reply Brief 2-
3.
Appellants further contend that:
The FIFO 7701 is not a “page frame memory” that stores
a “page of data” as claimed. Shishizuka explains that FIFO
7701 only holds 64 bits of data: “FIFO 7701 which has a
capacity of 512 bytes (64 bits_64).” (col. 44, lines 18-19). As
is known in the art, it is impossible for a “page of data” that
comes from a scanned image to fit in a 512 byte capacity
buffer. The present specification describes example pages of
data as “a 105 MB [megabyte] color page”, which after
compression may be 21 megabytes (page 6, [0021], “21 MB”).
The present specification also describes the page frame memory
in terms of megabytes as being “64 MB” to store “a single
compressed page” (page 6, [0023]). Therefore, one of ordinary
skill in the art would not understand the FIFO buffer 7701,
which holds only 512 bytes, to be a “page frame memory” that
can store “a page of data” as claimed. The FIFO buffer is not
configured to store a page of data and does not provide the
function of storing a page of data. Even more relevant is that
none of the components, circuits or busses that use the FIFO
buffer 7701 is configured to process a “page of data” as a unit
or store a page of data in the FIFO buffer 7701.
Reply Brief 3.

App
App

imag
whic
in re
Shis
page
page
have
the s
eal 2009-0
lication 10
Figur

“The] c
e data to t
h controls
We find
gards to di
hizuka’s d
frame me
or plane”
been obvi
ize of a pa
09292
/669,247
Shishizu
e 77 show
ontroller c
he printer
the FIFO.
Appellant
sclosing a
eficiencies
mory whic
of data. A
ous to com
ge frame m
ka’s figure
s a block d
FIFO co
onsists of
by way of
” See Shi
s’ argumen
page fram
. The Exa
h can be c
nswer 37
bine Shis
emory to
8
77 is repr
iagram of
ntroller 6
a FIFO wh
the GBI (G
shizuka, co
ts to be p
e memory
miner arg
onfigured
. The Exa
hizuka and
store an a
oduced be
a printer i
603.
ich is a bu
bus/B bu
lumn 44,
ersuasive.
and West
ues that W
to store “a
miner con
Westerve
mount of d
low:
mage data
ffer to tra
s I/F) and
lines 14-1
Shishizu
ervelt fails
estervelt d
scanline,
cludes that
lt and thu
ata to ma
transfer
nsfer
a circuit
8.
ka is silent
to addres
iscloses a
band,
it would
s configur
intain a

s

e
Appeal 2009-009292
Application 10/669,247

9
balance between a level of system performance for the intended imaging
mechanism and system cost. Answer 7-8.
However, we do not find a correlation between the two references that
would have lead one of ordinary skill in the art to modify either reference in
view of the other one. “It is impermissible to use the claimed invention as
an instruction manual or ‘template’ to piece together the teachings of the
prior art so that the claimed invention is rendered obvious.” In re Fritch,
972 F.2d 1260, 1266 (Fed. Cir. 1992) (quoting In re Gorman, 933 F.2d 982,
987 (Fed. Cir. 1991)). Consequently, “there must be some articulated
reasoning with some rational underpinning to support the legal conclusion of
obviousness.” In re Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006) (citing In re
Lee, 277 F.3d 1338, 1343-46 (Fed. Cir. 2002); In re Rouffet, 149 F.3d 1350,
1355-59 (Fed. Cir. 1998)). Absent some “articulated reasoning,” it follows
that the Examiner relied upon Appellants’ invention as a road map to
combine the two references thereby employing impermissible hindsight.
Therefore, we will not sustain the Examiner’s rejection of independent
claims 1 and 11 as well as their respective dependent claims 2-10 and 12-16.
Although claim 17 does not recite “a page frame memory” by name,
the recitation of first and second memories in conjunction with storage,
loading and transmitting “page of data” are merely broad claim terminology
that still distinguishes over the cited art. Therefore, we will not sustain the
Examiner’s rejection of independent claim 17 as well as dependent claims
18-23.

Appeal 2009-009292
Application 10/669,247

10
DECISION
The rejections of claims 1-23 under the various 35 U.S.C. § 103
rejections are reversed.

REVERSED

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