Ex Parte Landin et al

Board of Patent Appeals and Interferences

Apr 7, 2011

10821372 (B.P.A.I. Apr. 7, 2011)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte ANDERS LANDIN, ROBERT E. CYPHER, and
ERIK E. HAGERSTEN
____________________

Appeal 2009-005676
Application 10/821,3721
Technology Center 2100
____________________

Before JOSEPH L. DIXON, LANCE LEONARD BARRY AND,
JAY P. LUCAS, Administrative Patent Judges.

LUCAS, Administrative Patent Judge.

DECISION ON APPEAL2

1 Application filed April 9, 2004. The real party in interest is Sun
Microsystems.
2 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, or for filing a request for rehearing,
as recited in 37 C.F.R. § 41.52, begins to run from the “MAIL DATE”
(paper delivery mode) or the “NOTIFICATION DATE” (electronic delivery
mode) shown on the PTOL-90A cover letter attached to this decision.

Appeal 2009-005676
Application 10/821,372

2
STATEMENT OF THE CASE
Appellants appeal from a final rejection of claims 1 to 32 under
authority of 35 U.S.C. § 134(a). The Board of Patent Appeals and
Interferences (BPAI) has jurisdiction under 35 U.S.C. § 6(b).

We reverse.
Appellants’ invention relates to a method for reading data in a multi-
node system while maintaining coherency across nodes (Spec. ¶ [0001]). In
the words of Appellants:
A popular architecture in commercial
multiprocessing computer systems is a shared
memory architecture in which multiple processors
share a common memory. In shared memory
multiprocessing systems, a cache hierarchy is
typically implemented between the processors and
the shared memory. In order to maintain the
shared memory model, in which a particular
address stores exactly one data value at any given
time, shared memory multiprocessing systems
employ cache coherency. Generally speaking, an
operation is coherent if the effects of the operation
upon data stored at a particular memory address
are reflected in each copy of the data within the
cache hierarchy. For example, when data stored at
a particular memory address is updated, the update
may be supplied to the caches that are storing
copies of the previous data. Alternatively, the
copies of the previous data may be invalidated in
the caches such that a subsequent access to the
particular memory address causes the updated
copy to be transferred from main memory.
….
Various embodiments of methods and
systems for using proxy transactions to read data
from a non-owning memory subsystem in a multi-
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node system are disclosed. In one embodiment, a
node includes several devices including a memory,
an active device, and an interface configured to
send and receive coherency messages on an inter-
node network coupling the node to another node,
as well as an address network and a data network.
In response to receiving a coherency message
requesting an access right to a coherency unit, the
interface is configured to send a first type of
address packet on the address network if the global
access state of the coherency unit within the node
is the modified state and a second type of address
packet otherwise. The memory is configured to
respond to receipt of the second type of address
packet by sending a data packet on the data
network, regardless of whether the memory
currently has an ownership responsibility for the
coherency unit.
….
In order to cause memory to respond to the
RTS while not removing ownership from the
device D2 that initiated the subsequent RTO, the
interface may use a special type of proxy read-to-
share (PRTS) address packet. In one embodiment,
there may be two types of proxy request packets.
One type may be used in non-gM nodes and the
other may be used in gM nodes. In this
description, gM-type packets are identified by an
“M” at the end of the packet identifier (e.g.,
PRTOM, PRTSM, and PIM) and non-gM-type
packets lack the “M” identifier (e.g., PRTO, PRTS,
and PI). The non-gM type of request packets may
cause memory to respond, even if it is not the
current owner, and not affect the ownership of
owning caches within a node. In contrast, the gM
type of packets cause owning active device to give
up ownership and are not responded to by non-
owning memory subsystems. Both classes of
address packets may invalidate shared copies if
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they correspond to a transaction that invalidates
shared copies (e.g., RTO, WS). Note that in some
embodiments, PRTS packets may be implemented
as PMR packets, as described below.

(Spec. ¶¶ [0003], [0011] and [0250]).
The following illustrates the claims on appeal:
Claim 1:
1. A system, comprising:

a node including an active device, a system
memory, and an interface
interconnected by an address network
and a data network that is separate
from the address network;

an additional node coupled to send a
coherency message to the interface in
the node via an inter-node network,
wherein the coherency message
requests an access right to a
coherency unit;

wherein in response to the coherency
message, the interface is configured to
send a first type of address packet on
the address network if a global access
state of the coherency unit in the node
is a modified state and to send a
second type of address packet on the
address network if the global access
state is not the modified state;

wherein in response to the second type of
packet, the system memory is
configured to send a data packet
corresponding to the coherency unit
on the data network, regardless of
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whether the system memory has an
ownership responsibility for the
coherency unit.

The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Liencres US 5,434,993 Jul. 18, 1995
Roy US 6,065,092 May, 16, 2000
Chandrasekaran US 6,970,872 B1 Nov. 29, 2005
(filed on Jul. 23, 2002)
REJECTIONS
The Examiner rejects the claims as follows:

Claims 1 to 32 stand rejected under 35 U.S.C. § 103(a) for being
obvious over Liencres in view of Chandrasekaran and Roy.

ISSUE
The issue is whether Appellants have shown that the Examiner erred
in rejecting the claims under 35 U.S.C. § 103(a). The issue specifically turns
on whether the references Liencres, Chandrasekaran and Roy teach use of
different types of address packets on an address network depending on the
state of a coherency unit.

FINDINGS OF FACT
The record supports the following findings of fact (FF) by a
preponderance of the evidence.
1. Appellants have invented a method and system for maintaining
coherency in a computer system comprising multiple nodes, so that the
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nodes are aware that data in a cache or other memory may be invalid
(Spec. ¶ [0053]). Coherency units perform this task and are alerted to
changes in state by coherency messages sent between interfaces in the
nodes (¶ [0175]). Within the node, different types of packets on address
busses alert the active devices of changes in ownership of the coherency
units (¶ [0250]).
2. The Liencres reference teaches a multi-node computer system, containing
cache control systems (Col. 6, ll. 39 to 61). Cache lines contain status
bits indicating if a cache line is valid, owned (modified and not written
back to main memory yet) or shared (Col. 3, ll. 50 to 55).
3. The Chandrasekaran reference teaches a technique for reducing latency in
a multi-node system by “optimistically reading” data that is not in cache,
on the chance that it will be valid (Col. 6, ll. 25 to 36).

PRINCIPLES OF LAW
Appellants have the burden on appeal to the Board to demonstrate
error in the Examiner’s position. See In re Kahn, 441 F.3d 977, 985-86
(Fed. Cir. 2006) (“On appeal to the Board, an applicant can overcome a
rejection [under § 103] by showing insufficient evidence of prima facie
obviousness or by rebutting the prima facie case with evidence of secondary
indicia of nonobviousness.”) (quoting In re Rouffet, 149 F.3d 1350, 1355
(Fed. Cir. 1998)).

Appeal 2009-005676
Application 10/821,372

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ANALYSIS
Arguments with respect to the rejection
of claims 1 to 32
under 35 U.S.C. § 103(a) [R1]

The Examiner has rejected the noted claims for being obvious over
Liencres in view of Chandrasekaran and Roy. Appellants have presented a
number of arguments (App. Br. 9 to 13).
We will focus on Appellants’ second argument, as it is dispositive of
the rejection. Appellants contend that the references, most notably the
Chandrasekaran reference, fail to teach key limitations of the independent
claims 1, 13 and 24. Chandrasekaran was cited by the Examiner for
teaching the limitation “wherein in response to the coherency message, the
interface is configured to send a first type of address packet on the address
network if a global access state of the coherency unit in the node is a
modified state and to send a second type of address packet on the address
network if the global access state is not the modified state.” (App. Br. 11,
top; Ans. 4, bottom to 5, top). We have considered the Chandrasekaran
reference at the locations cited by the Examiner, and in its entirety, and fail
to find a teaching of two types of address packets as indicated by the claim
language. We further fail to find in the reference a teaching of the
coherency unit as claimed. And we further find no teaching of the
ownership of a coherency unit as claimed. As the Appellants indicate,
Chandrasekaran discloses an optimistic “read ahead” operation in which the
data is retrieved and then checked for validity (App. Br. 12, middle). The
claimed limitations are not addressed.
We find that the Appellants have indicated error in the Examiner’s
rejection, which reaches all of the claims.
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CONCLUSIONS OF LAW
Based on the findings of facts and analysis above, we conclude that
Appellants have shown that the Examiner erred in rejecting claims 1 to 32.

DECISION
We reverse the Examiner’s rejection of claims 1 to 32 under 35
U.S.C. § 103(a).
REVERSED

peb

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