Ex Parte Lai et al

Board of Patent Appeals and Interferences

Jul 19, 2011

11077479 (B.P.A.I. Jul. 19, 2011)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte LI-SHYUE LAI, HUNG-WEI CHEN,
WEN-CHIN LEE, and MIN-HWA CHI
____________

Appeal 2009-009776
Application 11/077,479
Technology Center 2800
____________

Before JOSEPH F. RUGGIERO, MAHSHID D. SAADAT, and
CARL W. WHITEHEAD, JR., Administrative Patent Judges.

RUGGIERO, Administrative Patent Judge.

DECISION ON APPEAL
Appeal 2009-009776
Application 11/077,479

2
STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) from the Final Rejection
of claims 1, 3-8, 14, and 18-20. Claims 2, 9-13, 15-17, and 21 have been
canceled. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.
Rather than reiterate the arguments of Appellants and the Examiner,
we refer to the Appeal Brief (filed August 29, 2008), the Answer (mailed
November 13, 2008), and the Reply Brief (filed January 13, 2009) for the
respective details. We have considered in this decision only those
arguments Appellants actually raised in the Briefs. Any other arguments
which Appellants could have made but chose not to make in the Briefs are
deemed to be waived. See 37 C.F.R. § 41.37(c)(1)(vii).

Appellants’ Invention
Appellants’ invention relates to a floating gate flash memory
structure. After source and drain implants are performed, source and drain
silicides are formed on the source and drain, respectively. A narrow space is
left between the source and a respective edge of the gate structure forming
an offset region. By applying the drain-source voltage to the narrow offset
region, avalanche breakdown will occur in the offset region and result in
reduced operating voltages and improved injection efficiency. See generally
Spec. ¶¶ [0009]-[0011].
Claim 1 further illustrates the invention and reads as follows:
1. A semiconductor device comprising:
a substrate;
a gate structure comprising:
Appeal 2009-009776
Application 11/077,479

3
a tunnel oxide over the substrate;
a floating gate over the tunnel oxide;
a dielectric over the floating gate; and
a control gate over the dielectric;
a first impurity region doped with a dopant of a first type laterally
spaced apart from a first edge of the gate structure;
a second impurity region doped with a dopant of a second type,
opposite from the first type, the second impurity region being substantially
under a spacer and substantially aligned with a second edge of the gate
structure; and
a first silicide on the first impurity region and a second silicide on the
second impurity region, wherein an inner edge of the first silicide is further
from a respective edge of the gate structure than an inner edge of the first
impurity region.

The Examiner’s Rejections
The Examiner’s Answer cites the following prior art references:
Sugiyama US 6,060,743 May 9, 2000
Hong US 6,096,605 Aug. 1, 2000
Chi US 6,143,607 Nov. 7, 2000
Buller US 6,967,363 B1 Nov. 22, 2005
(filed Oct. 1, 2003)
Claims 1, 3-5, 14, 18, and 20 stand rejected under 35 U.S.C. § 103(a)
as being unpatentable over Hong in view of Chi and Buller.
Claims 6-8 and 19 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Hong in view of Chi, Buller, and Sugiyama.

ANALYSIS
Claims 1 and 3-5
Appellants’ arguments with respect to the obviousness rejection of
independent claim 1 initially focus on the contention that, while the
Appeal 2009-009776
Application 11/077,479

4
Examiner has proposed combining Chi with Hong to cure Hong’s deficiency
in disclosing source and drain regions of opposite conductivity types, an
ordinarily skilled artisan would have no motivation to make such a
combination. Appellants’ arguments (App. Br. 9-11; Reply Br. 4-5) direct
attention to the portions of Chi at column 6, lines 17-23, and column 7, lines
63-65, as well as the illustration in Figure 13 of Chi, which, in Appellants’
view, suggest the importance of having the source and drain regions overlap
the gate structure. According to Appellants, this teaching conflicts with
Hong’s disclosure that one of the source/drain regions is spaced apart from
the gate structure edge.
We do not agree with Appellants. It is apparent to us from the
Examiner’s stated position (Ans. 4, 6-7) that the Examiner is not suggesting
the bodily incorporation of the ETOX cell of Chi into the flash memory
device of Hong. Rather, it is Chi’s teaching (col. 6, ll. 2-10) of the
advantage of reduced cell size resulting from the use of source and drain
regions of opposite conductivity types that is relied upon as a rationale for
the proposed combination with Hong. “The test for obviousness is not
whether the features of a secondary reference may be bodily incorporated
into the structure of the primary reference . . . . Rather, the test is what the
combined teachings of the references would have suggested to those of
ordinary skill in the art.” See In re Keller, 642 F.2d 413, 425 (CCPA 1981);
In re Nievelt, 482 F.2d 965, 968 (CCPA 1973).
We also find unpersuasive Appellants’ contention (App. Br. 11-12)
that the gate structure of Hong encompasses the entire illustrated area of
Hong’s Figure 2E (reproduced at page 8 the Appeal Brief) and, therefore,
Hong’s impurity region 27b overlaps and underlies the gates structure and is
Appeal 2009-009776
Application 11/077,479

5
not spaced apart from a gate edge as claimed. We find no basis for this
assertion by Appellants. As explained by the Examiner (Ans. 7-8),
conductive layer 32 is an interconnect line which connects the multiple cells
in the memory and it is only that part of the interconnect line that lies over
the floating gate that can reasonably be considered part of each cell gate
structure. We also agree with the Examiner that this latter interpretation of a
cell gate structure is consistent with what Appellants have described in the
Specification and illustrated, for example, in Figure 6 of the drawings.
For the above reasons, we sustain the Examiner’s 35 U.S.C. § 103(a)
rejection of independent claim 1, as well as dependent claims 3-5 not
separately argued by Appellants.

Claims 14, 18, and 20
We also sustain the Examiner’s obviousness rejection of claims 14,
18, and 20. Independent claim 14, with slightly different wording, sets forth
the same source/drain offset features as recited in previously discussed
independent claim 1. Appellants’ arguments (App. Br. 12) direct attention
to the claim 14 requirement that the gate structure overlies “a portion, but
not all” of the channel region (emphasis omitted).
According to Appellants (App. Br. 12), the gate structure of Hong
covers the entire illustrated area of Hong’s Figure 2E (reproduced at page 8
of the Appeal Brief) and, as such, Hong’s gate structure overlies the entire
channel region, not just a portion as claimed. This argument, however,
merely reiterates the argument made against the rejection of independent
claim 1. As we discussed supra, we find no basis for Appellants’
interpretation of the extent of the gate structure of Hong.
Appeal 2009-009776
Application 11/077,479

6
We further note that, for the first time in the Reply Brief (pages 5-6),
Appellants present arguments with respect to independent claim 14 that
allege error in the Examiner’s identification of the polysilicon layer 22 of
Hong as a floating gate. According to Appellants, the silicon nitride spacer
29a of Hong is in actuality the floating gate and, therefore, Hong’s gate
structure overlies the entirety of the channel region in contradistinction to
what is claimed.
This new argument is entitled to no consideration because it is not
responsive to a new point in the Answer in which the grounds of rejection of
claim 14 are repeated verbatim from the final Office action. See Ex parte
Borden, 93 USPQ2d 1473, 1473-74 (BPAI 2010) (“informative”1) (absent a
showing of good cause, the Board is not required to address an argument
newly presented in the Reply Brief that could have been presented in the
principal Brief on Appeal).

Claims 6-8 and 19
The Examiner’s obviousness rejection, based on the combination of
Hong, Chi, Buller, and Sugiyama, of dependent claims 6-8 and 19 is also
sustained. We find no error in the Examiner’s application of Sugiyama’s
SOI nano-island structure teaching (Figs. 14A-14D; col. 18, ll. 1-2) to the
combination of Hong, Chi, and Buller. Appellants’ arguments (App. Br. 13)
reiterate those asserted against independent claims 1 and 14, which
arguments we have found to be unpersuasive as previously discussed.

1 Designated as “Informative Opinion” at
http://www.uspto.gov/ip/boards/bpai/decisions/inform/index.jsp.
Appeal 2009-009776
Application 11/077,479

7
CONCLUSION OF LAW
Based on the analysis above, we conclude that the Examiner did not
err in rejecting claims 1, 3-8, 14, and 18-20 for obviousness under 35 U.S.C.
§ 103(a).

DECISION
We affirm the Examiner’s decision rejecting claims 1, 3-8, 14, and 18-
20 under 35 U.S.C. § 103(a).
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv) (2010).

AFFIRMED

babc