Ex Parte Kwong et al

Board of Patent Appeals and Interferences

Jan 31, 2012

11488799 (B.P.A.I. Jan. 31, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/488,799 07/19/2006 Herman Kwong 57983.000315 9469
21967 7590 01/31/2012
HUNTON & WILLIAMS LLP
INTELLECTUAL PROPERTY DEPARTMENT
2200 Pennsylvania Avenue, N.W.
WASHINGTON, DC 20037
EXAMINER
CHEN, XIAOLIANG
ART UNIT PAPER NUMBER
2835
MAIL DATE DELIVERY MODE
01/31/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte HERMAN KWONG, LUIGI DIFILIPPO, GUY DUXBURY,
and LARRY MARCANTI
____________

Appeal 2010-000249
Application 11/488,799
Technology Center 2800
____________

Before LANCE LEONARD BARRY, ST. JOHN COURTENAY III, and
ANDREW J. DILLON, Administrative Patent Judges.

DILLON, Administrative Patent Judge.

DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 1-8. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

STATEMENT OF THE CASE
Appellants’ invention is directed to an integrated circuit device for
accommodating electronic components on a multilayer signal routing device.
A plurality of electrically conductive pads formed on a primary surface are
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Application 11/488,799

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electrically connected via a group of conductive micro-vias to a channel on a
secondary surface which accommodates an electronic component mounted
on that surface. See Abstract.

Claim 1 is illustrative, with key disputed limitations emphasized:
1. A multilayer signal routing device comprising:

a primary surface having a plurality of electrically
conductive pads formed thereon, a group of the plurality of
electrically conductive pads in respective electrical connection
with a group of electrically conductive micro-vias formed in the
multilayer signal routing device; and

a secondary surface having a channel formed thereon, the
channel having a channel area on the secondary surface for
accommodating an electronic component mounted on the secondary
surface;

wherein the group of electrically conductive micro-vias
extend from the primary surface into the multilayer signal
routing device, but not entirely through the multilayer signal
routing device to the secondary surface;

wherein the channel is formed on the secondary surface
directly beneath where the group of electrically conductive
micro-vias extend from the primary surface into the multilayer
signal routing device.

The Examiner relies on the following as evidence of unpatentability:
Haller US 5,357,403 Oct. 18, 1994
Takeuchi US 2002/0008314 A1 Jan. 24, 2002
(filed Apr. 13, 2000)

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Application 11/488,799

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THE REJECTIONS
1. The Examiner rejected claims 1-8 under 35 U.S.C. § 112, first
paragraph as failing to comply with the written description
requirement. Ans. 3-4.1
2. The Examiner rejected claims 1-8 under 35 U.S.C. §103(a) as
unpatentable over Takeuchi and Haller. Ans. 5-9.

CONTENTIONS
Regarding claim 1, the only independent claim in the present appeal,
the Examiner finds that the claim limitation which recites “wherein the
group of electrically conductive micro-vias extend from the primary surface
into the multilayer signal routing device, but not entirely through the
multilayer signal routing device to the secondary surface” was not described
in the Specification in such a way to reasonably convey to one skilled in the
relevant art that the inventor(s), at the time the application was filed, had
possession of the claimed invention. Ans. 3-4.
The Examiner also finds that Takeuchi discloses a multilayer signal
routing device having a primary surface with a plurality of conductive pads,
(Ans. 5), a group of electrically conductive micro-vias formed in the
multilayer signal routing device and a secondary surface having a channel
formed thereon for accommodating an electronic component. (Id. at 6.) The
Examiner acknowledges that Takeuchi does not disclose that some of the

1 Throughout this opinion, we refer to the Appeal Brief filed April 13, 2009,
the Examiner’s Answer mailed June 19, 2009, and the Reply Brief filed
August 19, 2009.
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Application 11/488,799

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micro-vias do not extend completely through the multilayer signal routing
device, (Id.) but cites Haller for a disclosure of a micro-via that does not
extend entirely through a multilayer signal routing device. Id. at. 6-7.
Appellants argue that their Specification contains written description
of micro-vias which recites that some of the electrical contacts on the
primary side of the multilayer signal routing device are not coupled to
conductive contacts on the secondary side of the multilayer signal routing
device. App. Br. 6-8.
Appellants argue that multiple related patents, which are incorporated
in their entirety within the present application by reference thereto, disclose
and illustrate micro-vias which do not entirely extend through the multilayer
signal routing device. Reply Br. 4-5.
Applicants also argue that Takeuchi fails to disclose “a secondary
surface having a channel formed thereon…” (App. Br. 11-12); that through-
holes 5 and 6 disclosed by Takeuchi are not “micro-vias” and are merely
formed through a printed wiring substrate (Reply Br. 8); and, that the
Examiner has inappropriately combined Takeuchi and Haller. Reply Br. 11-
12.
The issues before us, then, are as follows:

ISSUES
1. Under § 112, has the Examiner erred in rejecting independent
claim 1 by finding that the claim limitation which recites “wherein the group
of electrically conductive micro-vias extend from the primary surface into
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Application 11/488,799

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the multilayer signal routing device, but not entirely through the multilayer
signal routing device to the secondary surface” was not described in the
Specification in such a way to reasonably convey to one skilled in the
relevant art that the inventor(s), at the time the application was filed, had
possession of the claimed invention?
2. Under § 103, has the Examiner erred in rejecting representative
claim 1 by finding that Takeuchi and Haller collectively would have taught
or suggested a multilayer signal routing device having a primary surface
with a plurality of conductive pads, a group of electrically conductive micro-
vias formed in the multilayer signal routing device and a secondary surface
having a channel formed thereon for accommodating an electronic
component wherein some of the micro-vias do not extend completely
through the multilayer signal routing device?
3. Is the Examiner’s reason to combine the teachings of these
references supported by articulated reasoning with some rational
underpinning to justify the Examiner’s obviousness conclusion?

FINDINGS OF FACT (FF)
We find that the following enumerated findings of fact are supported
by at least a preponderance of the evidence. Ethicon, Inc. v.
Quigg, 849 F.2d 1422, 1427 (Fed. Cir. 1988) (explaining the general
evidentiary standard for proceedings before the Office).
1. U. S. Patent No. 6,388,890, inter alia, incorporated by reference in
its entirety within the present application, (Specification, 1)
discloses and illustrates a micro-via 26, which terminates without
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extending entirely through a multilayer signal routing device. U.S.
Patent No. 6,388,890, Figure 1, element 26; col. 4, ll. 25-44.
2. Appellants’ Figure 2A is reproduced below:
Appellants’ Figure 2A illustrates “multiple additional electronic
components 106A” mounted on a secondary side of the multilayer
signal routing device. Specification, p. 19, ll. 2-7 (describing
Figure 2A).
3. Takeuchi discloses a semiconductor integrated circuit having
conductive pads disposed on opposite sides thereof and through-
holes disposed therein for conductive connection between both
sides of the semiconductor integrated circuit. Takeuchi, Abstract.
4. Haller discloses via holes, such as via 54, which terminate within
the integrated circuit and do not extend entirely through the
integrated circuit. Haller, col. 9, ll. 32-64 (describing Figure 2).

ANALYSIS
The § 112 Rejections
The Examiner has rejected claims 1-8 under 35 U. S. C. § 112, first
paragraph as failing to comply with the written description requirement.
Specifically, the Examiner finds that the limitation within representative
claim 1which recites “wherein the group of electrically conductive micro-
vias extend from the primary surface into the multilayer signal routing
device, but not entirely through the multilayer signal routing device to the
secondary surface” was not described in the Specification in such a way to
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Application 11/488,799

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reasonably convey to one skilled in the relevant art that the inventor(s), at
the time the application was filed, had possession of the claimed invention.
Similarly, the Examiner also finds that the limitation added by amendment
to claim 8, i.e. “a packaged integrated circuit electronic component” was not
adequately described in the Specification. Ans. 3-4.
Appellants argue that U.S. Patent Nos. 6,388,890; 6,545,876;
7,069,646; and 7,069,650, each of which was incorporated by reference in
its entirety within the present application, satisfies the written description for
the disputed element within claim 1. Reply Br. 4-5. Additionally, Appellants
argue that the “packaged integrated circuit electronic component” set forth
within claim 8 is illustrated within Figure 2A and is adequately described
within Appellants’ Specification. App. Br. 8-9; Reply Br. 5-7.
We find that the incorporated United States patents set forth above,
including U.S. Patent No. 6,388,890, describe micro-vias which “extend
from the primary surface into the multilayer signal routing device, but not
entirely through the multilayer signal routing device to the secondary
surface,” as set forth in representative claim 1. (FF1).
It is well-settled that “essential material,” that is, material which is
necessary to provide a written description of the claimed invention, may be
incorporated by reference to a United States patent or a United States patent
application publication. See 37 C.F.R. §1.57(c)(1).
Further, we find that Appellants’ illustration of “multiple additional
electronic components 106A” within Figure 2A appears to illustrate
graphically a packaged integrated circuit electronic component within their
specification. (FF2).
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Consequently we find the Examiner erred in rejecting claims 1-8
under 35 U.S.C. §112, first paragraph, for failing to comply with the written
description requirement.
The § 103 Rejections
The Examiner finds that Takeuchi discloses a multilayer signal
routing device having a primary surface with a plurality of conductive pads,
(Ans. 5) a group of electrically conductive micro-vias formed in the
multilayer signal routing device and a secondary surface having a channel
formed thereon for accommodating an electronic component. (Id. at 6).The
Examiner acknowledges that Takeuchi does not disclose that some of the
micro-vias do not extend completely through the multilayer signal routing
device, (Id.) but cites Haller for a disclosure of a micro-via that does not
extend entirely through a multilayer signal routing device. Id. at 6-7.
Appellants argue that Takeuchi fails to disclose “a secondary surface
having a channel formed thereon…” App. Br. 11-12; Reply Br. 7-8. Further,
Appellants argue that Takeuchi fails to disclose a group of electrically
conductive micro-vias which extend from the primary surface into the
multilayer signal routing device, but not entirely through the multilayer
signal routing device to the secondary surface, as set forth in claim 1,
arguing that the through-holes disclosed in Takeuchi are merely formed
through a printed wiring substrate. App. Br. 12; Reply Br. 8.
[D]uring examination proceedings, claims are given their broadest
reasonable interpretation consistent with the specification. In re Hyatt, 211
F.3d 1367, 1372 (Fed. Cir. 2000).
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We find that Takeuchi discloses conductive mounting pads on a
secondary surface, (FF3), which we conclude is a reasonable interpretation
of “a channel area on the secondary surface for accommodating an electronic
component mounted on the secondary surface” as set forth in claim 1.
We find that Haller discloses so-called “blind vias” such as via 54,
which terminate within the integrated circuit and do not extend entirely
through the integrated circuit. (FF4).
We also find the Examiner has articulated a rational basis for
combining the Takeuchi and Haller references, noting that rearranging parts
of an invention involves only routine skill in the art. Ans. 7. We find that
Takeuchi and Haller are both directed to the construction of integrated
circuit devices and we find no error in the Examiner’s proposed combination
of these two references.
Appellants separately list features recited within each of claims 2-8
and merely urge that such features are not shown within the cited references.
In In re Lovin, 652 F.3d 1349, 1352 (Fed. Cir. 2011) the Federal
Circuit held that a mere recitation of the claim elements and a naked
assertion that the corresponding elements were not found in the prior art is
not sufficiently substantive to comply with Rule 41.37.
Consequently we find that Appellants have not separately argued
claims 2-8 with sufficient particularity.
We are therefore not persuaded that the Examiner erred in rejecting
claim 1 and claims 2-8, not separately argued with particularity, as
unpatentable under §103.

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Application 11/488,799

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CONCLUSION
The Examiner erred in rejecting claims 1-8 under § 112, first
paragraph as failing to comply with the written description requirement.
The Examiner did not err in rejecting claims 1-8 under § 103.
ORDER
The Examiner’s decision rejecting claims 1-8 under § 112, first
paragraph is reversed.
The Examiner’s decision rejecting claims 1-8 under § 103 is affirmed.
Because we have affirmed at least one ground of rejection with
respect to each claim on appeal, the Examiner’s decision is affirmed.
See 37 C.F.R. § 41.50(a)(1).
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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