Ex Parte Kurtz

Patent Trial and Appeal Board

Jan 16, 2015

12414397 (P.T.A.B. Jan. 16, 2015)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte ROBERT G. KURTZ
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Appeal 2012-001461
Application 12/414,397
Technology Center 2100
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Before JOSEPH L. DIXON, JAMES R. HUGHES, and ERIC S. FRAHM,
Administrative Patent Judges.

FRAHM, Administrative Patent Judge.

DECISION ON APPEAL
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner’s
rejections of claims 1–7 and 9–21. App. Br.4; Ans. 3. Claim 8 is canceled.
Id. Claims 18–21 are allowed. Id. We have jurisdiction under 35 U.S.C.
§ 6(b).
We affirm.

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PRIOR ART
The Examiner relies upon the following prior art in rejecting the
claims on appeal.
Campbell US 6,286,088 B1 Sept. 4, 2001
Raut US 2005/0240747 A1 Oct. 27, 2005
Abrashkevich US 7,181,585 B2 Feb. 20, 2007
REJECTIONS
The Examiner rejected claims 1–7, 9–11, and 13–17 under the
judicially-created doctrine of double patenting over claims 1–10 of Kurtz
(U.S. Patent No. 7,512,765 B2; issued Mar. 31, 2009). Ans. 4–7.
The Examiner rejected claims 1–3, 6, 9, and 12 under 35 U.S.C.
§ 103(a) as unpatentable over Raut, Abrashkevich, and Campbell. Id. at 8–
12.
The Examiner rejected claim 14 under § 103(a) as unpatentable over
Raut and Abrashkevich. Id. at 12–14.
DOUBLE PATENTING REJECTION
Appellant “postpone[s]” addressing the double patenting rejection;
choosing to file a terminal disclaimer, at the close of prosecution, if needed
despite future prosecution (e.g., despite future amendments). Reply Br. 2;
see also App. Br. 17 (“Appellant is willing to file a terminal disclaimer”).
The double patenting rejection is accordingly sustained in view of
Appellant’s failure to present any substantive arguments in response to the
Examiner’s prima facie case of double patenting of claims 1–7, 9–11, and
13–17 on appeal over claims 1–10 of Kurtz (see Ans. 4–7).
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OBVIOUSNESS REJECTIONS
Appellant addresses claims 1–3, 6, 9, 12, and 14 collectively. App.
Br. 17–22. We address the arguments with reference to claim 1, reproduced
below. See, e.g., 37 C.F.R. § 41.37(c)(1)(iv) (representative claims).1
1. A method of auditing memory in a system, the method
comprising:
receiving a memory request from an application;
populating a memory tag having a stack depth component and a
traceback stack component, the traceback stack component
containing a pointer to a traceback stack, the stack depth
component defining a size of the traceback stack, and the
traceback stack containing information from a program stack
associated with the application;
determining if a memory pool has enough free memory to
satisfy the request for memory; and
allocating, from a memory pool, a memory allocation unit with
a header, a data area, and a footer, the data area defining an area
to which the application may write data, and the footer
bounding the data area with a special code.

1 Claims 1 and 14 are the only independent claims on appeal (independent
claim 18 is allowed and not appealed). Though claims 1 and 14 are
addressed under separate headings, Appellant states that claim 14 is
allowable “for substantially similar reasons to those discussed above with
respect to independent Claim 1.” App. Br. 21–22. We therefore view the
arguments for claims 1 and 14 (and their dependent claims) as being
substantively identical. If Appellant views the arguments as differing for
claims 1 and 14, the difference/s should have been (but were not)
meaningfully explained. See, e.g., In re Baxter Travenol Labs, 952 F.2d
388, 391 (Fed. Cir. 1991) (“It is not the function of this court to examine the
claims in greater detail than argued by an appellant[.]”).
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Appellant argues that the applied prior art does not teach or suggest
claim 1’s “populating” step. App. Br. 18–22.
The Examiner finds that Raut’s Figure 2A embodiment and
Abrashkevich’s Figures 3–4 embodiments suggest the populating step in
several principal respects. Ans. at 20–21.
Addressing claim 1’s “traceback stack containing information from a
program stack,” the Examiner finds Raut’s memory leak table 208 teaches
the “traceback stack” insofar that each entry 220 records a call path. Id. at
20.
Addressing claim 1’s “memory tag having . . . a traceback stack
component . . . containing a pointer to a traceback stack,” the Examiner finds
the header of Raut’s memory block 203 teaches the “memory tag” and
“traceback stack component” insofar as including a pointer to the table 208.
Id.
Addressing claim 1’s “memory tag having a stack depth component
. . . defining a size of the traceback stack,” the Examiner presents two
findings. First, Raut suggests storing such size information insofar as stating
the table 208 can be bounded in size (e.g., by a hash function). Id. at 21.
Second, Abrashkevich suggests storing the size information within the
header of Raut’s memory block 203 (cited as teaching claim 1’s “stack depth
component”) insofar as stating that a size of allocated memory may be
stored within headers, e.g., within skip lists illustrated by Abrashkevich’s
Figures 3 and 4. Id.
Appellant’s arguments fail to address the above combination of
teachings; that is, the particularly proposed modification of Raut’s Figure 2A
embodiment in view of Abrashkevich. Notably, though the Answer’s
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“Response to Arguments” section summarizes the combination within a
“Conclusion” subsection (at pages 20–21), the Reply Brief arguments never
even cite to the “Conclusion” subsection. Apparently overlooking the
“Conclusion” subsection, Appellant repeatedly mischaracterizes the
Examiner’s reliance on Raut and Abrashkevich.
For example, Appellant mischaracterizes the rejection of claim 1 as
stating that Raut’s cited header “includes the size indicator.” Reply Br. 3
(citing Ans. 8). Though the Answer indeed states “[Raut’s] header shown in
Fig. 2A . . . includes the size indicator” (Ans. 8), the Answer’s “Conclusion”
subsection clarifies that the Examiner particularly finds Raut suggests
storing the size of a “traceback stack” (specifically) and Abrashkevich
suggests storing the size of allocated memory (generally) within a related
header. See supra.
In addition to addressing claim 1’s “populating” step, Appellant
contends that Raut’s cited header is not a “memory tag.” Reply Br. 6. The
ensuing comments attempt to rewrite the rejection instead of presenting, as
needed, a required feature of claim 1’s “memory tag” that patentably
distinguishes the claimed invention. See, e.g., id. (“[T]o the extent the
header of Raut can be equated to anything in the claims, it would be the
header of the memory allocation unit[.]”). The ensuing comments also again
mischaracterize the Examiner’s proposed combination of Raut’s and
Abrashkevich’s teachings. See, e.g., id. at 7 (stating the combination
modifies Raut’s Figure 2A embodiment so as to bodily incorporate
Abrashkevich’s cited header).
In light of the foregoing deficiencies, Appellant’s arguments are not
persuasive of error in the Examiner’s conclusion of obviousness.
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Accordingly, the obviousness rejections of claims 1–3, 6, 9, 12, and 14 are
sustained.
DECISION
The Examiner’s decision rejecting claims 1–7 and 9–21 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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