Ex Parte Kubo et al

Board of Patent Appeals and Interferences

Feb 24, 2011

10716791 (B.P.A.I. Feb. 24, 2011)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/716,791 11/19/2003 Hiroaki Kubo JP920020167US1 6146
55315 7590 02/24/2011
ANNE VACHON DOUGHERTY
3173 CEDAR ROAD
YORKTOWN HTS., NY 10598
EXAMINER
WERNER, DAVID N
ART UNIT PAPER NUMBER
2483
MAIL DATE DELIVERY MODE
02/24/2011 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte HIROAKI KUBO and MASAHIRO MURAKAMI
____________

Appeal 2009-014002
Application 10/716,791
Technology Center 2600
____________

DECISION ON APPEAL1

Before RICHARD TORCZON, KARL D. EASTHOM, and STEPHEN C.
SIU, Administrative Patent Judges.

EASTHOM, Administrative Patent Judge.

1 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, or for filing a request for rehearing,
as recited in 37 C.F.R. § 41.52, begins to run from the “MAIL DATE”
(paper delivery mode) or the “NOTIFICATION DATE” (electronic delivery
mode) shown on the PTOL-90A cover letter attached to this decision.
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STATEMENT OF THE CASE
Appellants appeal2 under 35 U.S.C. § 134 from the rejection of claims
1-7. (App. Br. 1.) We have jurisdiction under 35 U.S.C. § 6(b).
We affirm-in-part.
The Disclosed Invention3
The disclosed invention includes a format conversion circuit that
inputs digital video data from a video decoder that converts an analog video
signal to the digital video data. (Spec. p. 6, ll. 11-13.) The circuit then
converts the format of the digital video data “to a pseudo MPEG2-TS
format.” (Spec. p. 6, ll. 11-13.) The circuit segments the digital video data
“into multiple segments that become payloads of MPEG2-TS data MD to be
output.” (Spec. p. 10, ll. 7-9.) “A packet header as defined by MPEG2-TS
is inserted immediately before each payload.” (Spec. p. 10, ll. 10-11.) The
circuit transfers the payload into a packet during a horizontal
synchronization period, a blank period during which no valid data exists at
the circuit’s input. (Spec. p. 10, ll. 14-16, 23-26.)
Exemplary claim 1 follows:
1. A format conversion circuit for conversion of
digitized video data comprising a plurality of lines of data with
a plurality of horizontal synchronization periods, one horizontal
synchronizing period following each line of data, comprising:
a memory for storing video data;
header generation device for generating a packet header
that adheres to a standard for motion picture compression;

2 Appellants’ Appeal Brief (filed December 9, 2008 (“App. Br.”) and Reply
Brief (filed May 13, 2009 )(“Reply Br.”), and the Examiner’s Answer
(mailed April 14, 2009) (“Ans.”) are referenced here.
3 The ensuing description constitutes findings of fact.
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synchronous timing detector for detecting a
synchronizing signal for a line of video data; and
selection device for repeating the selection of the packet
header generated by said header generation means and
selection of a predetermined amount of video data read
out of said memory as a payload responsive to the packet
header, during an interval from when said synchronous timing
detection device detects the synchronizing signal for the line of
data until it detects the next synchronizing signal at a start of a
next successive line of data, whereby for each line of data, the
selection of video data is completed during the horizontal
synchronizing period following that line of data.
The Examiner relies on the following prior art references:
Yamauchi US 5,671,260 Sep. 23, 1997
Settle US 6,233,253 May 15, 2001
Tsubouchi US 6,297,794 Oct. 2, 2001
Chernock, Richard S., Data Broadcasting: Understanding the ATSC Data
Broadcast Standard (McGraw-Hill 2001) [hereinafter Chernock].

International Standard ISO/IEC 13818-1, Information technology — Generic
coding of moving pictures and associated audio information: Systems,
Dec. 1, 2000 [hereinafter ISO/IEC 13818-1].

Claims 1-7 stand rejected under 35 U.S.C. 103(a) based on Tsubouchi,
Settle and Yamauchi.
ISSUES
Appellants’ responses to the Examiner’s positions present the
following issues:
1. Did the Examiner err in finding that the combination of Tsubouchi,
Settle and Yamauchi renders obvious the limitations of a) storing digitized
video data, b) “detecting a synchronizing signal for a line of video data,” and
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c) “repeating the selection of the packet header generated by said header
generation means and selection of a predetermined amount of video data
read out of said memory as a payload” during an interval between the
detection of the synchronizing signals for one line of data and the next line
of data whereby “the selection of video data is completed during the
horizontal synchronizing period,” as recited in claim 1, and as similarly
recited in claims 6, and 7?
2. Did the Examiner err in finding that the combination of Tsubouchi,
Settle and Yamauchi renders obvious a counter for counting the amount of
packet header and video data and a switch for selecting the packet header or
video data, as recited in claim 2?
3. Did the Examiner err in finding that the combination of Tsubouchi,
Settle and Yamauchi renders obvious the limitations of a) converting the
format of digitized video data “to a pseudo MPEG2-TS format” and b) “a
FIFO memory for storing the video data in response to a clock for the video
data,” as recited in claim 3?
4. Did the Examiner err in finding that the combination of Tsubouchi,
Settle and Yamauchi renders obvious claims 4 and 5?
FINDINGS OF FACT (FF)
Tsubouchi
1. Tsubouchi teaches a system comprising a variety of video devices,
a video/audio dedicated bus, and a display controller. (Abstract.) Motion
pictures from the variety of video devices can be efficiently displayed
because “any motion-picture source can be transferred directly to a display
controller.” (Id.) The variety of video devices include a PC card controller,
a MPEG2 decoder, an MPEG encoder, a video capture, etc. (Abstract;
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col. 2, ll. 33-39; col. 6, ll. 50-58.) The video capture performs the step of
“[c]onverting analog video signals from an imaging device such as a video
camera to digital data, and inputting the digital data.” (Col. 1, ll. 45-47.)
“Each video device has an output buffer for outputting motion-picture data
from the output port to the video/audio dedicated bus.” (Col. 2, ll. 55-57.)
2. Each of the video devices requests access to the video/audio
dedicated bus by transmitting a pulse on a control line and accesses the bus
after its flip-flop is enabled:
In the device 1, the pulse generating circuit 601 outputs a
one-shot pulse signal ZV-EN1 when the enable flag F1 is set.
The one-shot pulse signal ZV-EN1 is supplied to the delay
circuit 602. It is also supplied, as a ZV control signal, onto the
ZV control signal line through the buffer 604. The
combinatorial logic circuits of all devices monitor the change in
the ZV control signal, which takes place at this time. In the
device 1, the flip-flop 603 is reset. In the device 2, the flip-flop
is reset, too. The enable/disable signal EN/DIS2 is thereby
disabled.
Upon lapse of the time corresponding to the width of the
one-shot pulse signal ZV-EN1, the display circuit 602 outputs a
set signal SET1. The set signal SET1 is supplied to the flip-
flop 603. The flip flop 603 changes the enable/disable signal
EN/DIS1 to 1, or activates the signal EN/DIS1, in response to
the set signal SET1.
(Col. 10, ll. 40-56.)
Settle
3. Settle discloses a conversion system for merging and converting
data “in a plurality of different data formats from a plurality of different
sources to a selected output data format for transmission on a selected
transmission channel.” (Abstract.) The system re-packetizes data that has
been depacketized, multiplexes the re-packetized data, and provides it to an
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output channel. (Id.) Header-less packets are “re-formatted to be in MPEG
compatible transport packet form.” (Col. 3, ll. 23-26.) Next, the reformatted
header-less packets “are re-aligned and added to new MPEG compatible
headers.” (Col. 3, ll. 26-29.)
Yamauchi
4. Yamauchi discloses an apparatus that converts an input analog
video signal to a digitized video signal and stores the digitized video signal
to a memory. (Abstract.)
5. The apparatus “extracts a horizontal synchronization signal
(H. sync.) and a vertical synchronization signal (V. sync.) from the video
signal SV to produce a composite synchronization signal SS.” (Col. 4,
ll. 44-50.) The apparatus “extracts the horizontal synchronization
components H. sync. from the composite sync signal SS to produce a first
reference signal Sf1 as a horizontal reference signal.” (Col. 4, ll. 53-56.)
A phase locked loop (PLL) unit “responds to the high frequency of the
horizontal reference signal Sf1, and produces a high speed clock signal Sc1
as a first clock signal.” (Col. 5, ll. 6-8.) The apparatus writes the digitized
video signal to memory based on the horizontal reference signal Sf1, the
high speed clock signal Sc1, and a write signal SW:
The high speed PLL 13 produces the high speed clock signal
Sc1 synchronized with the H. Sync. signal of the input video
signal SV… By using the high speed clock signal Sc1, the
analog input video signal SV is converted into a digital signal,
and is stored into the video memory 6.
(Col. 8, ll. 18-28.)
6. The apparatus calculates the effective data in the input video signal
and produces a signal indicative of the calculated effective data:
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The write controller 7 calculates the effective data in the video
signal SV based on the vertical and horizontal reference signals
Sf1 and Sf2 with respect to the clock signal Sc1. For example,
when the video signal SV conforms to the NTSC system, the
effective data corresponds to the range starting from lines 23 to
262, and from lines 285 to 524, and the range from 123 to 842
samples are counted from the trailing edge of the horizontal
reference signal Sf1. Then, the write controller 7 produces the
write signal SW, indicative of the calculated effective data.
(Col. 5, ll. 17-26.)
7. The apparatus references the write signal SW to write the effective
data to memory:
Referring to FIG. 3, the relationship between the
horizontal reference signal Sf1, the high speed clock signal Sc1,
and the writing signal SW around the effective data area, lines
23 and 24 for example, is depicted on an enlarged scale…
In this example, the high speed clock signal Sc1 counts
858 clocks for the period T1. Within this period T1, the writing
signal SW controls the video memory 6 to write the data from
the A/D converter 5 therein as follows.
After passing the first 122 clocks, the writing signal SW
controls the memory 6 to store the data for the next 720 clocks.
(Col. 8, ll. 1-14.)
“Thereafter, the memory 6 is released for the last 16 clocks.” (Col. 8,
ll. 15-16.)
Chernock
8. “An MPEG-2 Transport Stream packet is 188 bytes in length.”
(P. 44.)
ISO/IEC 13818-1
9. The packet header of a transport steam packet may be followed by
a payload or an adaptation field. (P. 20.) A two-bit field indicates whether
the “packet header is followed by an adaptation field and/or payload.” (Id.)
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A field called the adaptation_field_length specifies “the number of bytes in
the adaptation_field immediately following the adaptation_field_length.”
(P. 21.) “For Transport Stream packets carrying PES packets, stuffing is
needed when there is insufficient PES packet data to completely fill the
Transport Stream packet payload bytes.” (Id.)
PRINCIPLES OF LAW
The Examiner bears an initial burden of factually supporting an
articulated rejection. In re Oetiker, 977 F.2d 1443 (Fed. Cir. 1992). Under
§ 103, “‘there must be some articulated reasoning with some rational
underpinning to support the legal conclusion of obviousness.’” KSR Int’l
Co. v. Teleflex, Inc., 550 U.S. 398, 418 (2007) (citation omitted). On appeal,
Appellant may rebut the Examiner’s findings and reasoning with opposing
evidence or argument. Failure to do so may constitute a waiver of potential
arguments. See Ex parte Frye, 94 USPQ2d 1072, 1075 (precedential) (BPAI
2010) (“If an appellant fails to present arguments on a particular issue — or,
more broadly, on a particular rejection — the Board will not, as a general
matter, unilaterally review those uncontested aspects of the
rejection.”); Hyatt v. Dudas, 551 F.3d 1307, 1313-14 (Fed. Cir. 2008) (The
Board may treat arguments appellant failed to make for a given ground of
rejection as waived); 37 C.F.R. § 41.37(c)(1)(vii).
ANALYSIS
Issue 1- Independent Claims 1, 6, and 7
Appellants assert that “the combined teachings of Settle, Tsubouchi,
and Yamauchi do not teach or suggest the claim features of storing video
data which has been digitized.” (App. Br. 16.) Appellants argue that
“neither Settle nor Tsubouchi teaches or suggests storing video data which
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has been digitized (i.e., converted in a video encoder from analog format to
digital format).” (App. Br. 12.) As found by the Examiner, however,
Tsubouchi teaches that each of a variety of video devices “includes an
output buffer for outputting data onto the bus.” (Ans. 4; accord FF 1.) As
also found by the Examiner, these video devices include devices that operate
on digital data, such as a video capture device, an MPEG-2 decoder, and an
IEEE 1394 controller. (Ans. 10; accord FF 1.) Because Tsubouchi
discloses video devices that operate on digital data and have a buffer (i.e., a
memory for storing this data), Tsubouchi teaches the claim feature of storing
digital video data.
Appellants also assert that the combination of Settle, Tsubouchi and
Yamauchi does not teach or suggest “detecting a synchronizing signal for a
line of the video data.” (App. Br. 16.) After acknowledging that Tsubouchi
teaches an enable signal, Appellants argue that the “Tsubouchi does not
teach or suggest that the enable signal is a synchronization signal.” (App.
Br. 12.) As explained by the Examiner, however, the enable signal of
Tsubouchi is a synchronization signal because it controls access to the
video-audio dedicated bus by the variety of video devices. (Ans. 5, accord
FF 2.) As explained in more detail by the Examiner, “a pulse generating
circuit in each device sends out a pulse on the control line to disable other
devices and free up the A/V bus for data transmission.” (Ans. 5, accord
FF 2). In other words, the video devices of Tsubouchi detect the
synchronization signal controlling access to the bus before writing video
data to the bus. Accordingly, the teachings of Tsubouchi render obvious the
claim feature of “detecting a synchronizing signal for a line of the video
data.”
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Appellants also assert that the combined teachings of Settle,
Tsubouchi, and Yamauchi do not teach or suggest the claim limitation of
“packetizing the video data.” (App. Br. 16-17; see also Reply Br. 2-5.) To
support their assertion, Appellants argue only that “Settle does not teach that
MPEG-2 packets be produced,” and that “Settle makes no mention of a fixed
packet length.” (App. Br. 10.) As found by the Examiner, however, Settle
discloses that header-less packets are re-formatted to be in MPEG
compatible transport packet form and are re-aligned and added to new
MPEG compatible headers. (Ans. 4; accord FF 3.) Moreover, as explained
by the Examiner, Settle states that the “packets are MPEG transport packets,
which inherently have a fixed length.” (Ans. 10; accord FF 3, 8, and 9.)
Appellants also argue that Yamauchi does not disclose the limitation
of selecting video data read from memory during the horizontal
synchronizing period as required by claim 1, but instead teaches “that a read
signal is produced based on the vertical synchronization signal, and not on a
horizontal synchronization.” (App. Br. 13.) Appellants also argue that
Yamauchi does not disclose this claim limitation but instead teaches
“writing video data into the memory in response to a signal.” (App. Br. 14.)
As explained by the Examiner, however, Yamauchi discloses that a write
signal is “controlled by the horizontal synchronization period.” (Ans. 10-11;
accord FF 4, 5.) In particular, Yamauchi’s apparatus writes the digitized
video signal to memory in accordance with signals that are derived from
horizontal synchronizing signals. (FF 5.) Moreover, contrary to Appellants’
argument, the write signal of Yamauchi is relevant to claim 1 even though
claim 1 refers to the selection of video data that is read from memory. As
explained by the Examiner, Yamauchi “demonstrate[s] that it was known in
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the art to use the horizontal synchronization of a raster video signal to
perform control operations of a buffer, with the result of not digitizing or
transmitting non-video data presented during the horizontal control period.”
(Ans. 11.)
In light of Yamauchi teaching that writing digitized video data to
memory may be controlled by horizontal synchronizing signals, it would
have been obvious to perform other operations on digitized video data (such
as selecting video data read out from memory as a payload as recited in
claim 1) in accordance with the horizontal synchronizing signals. Moreover,
in light of Yamauchi’s teachings that video data is not presented as input
during the horizontal blanking period and therefore, need not be read during
that period, it would have been obvious to perform other tasks during that
period, such as selecting video data from memory as a payload.
Therefore, we will sustain the Examiner’s rejection of claim 1. We
will also sustain the Examiner’s rejections of independent claims 6 and 7
because Appellants did not present any patentability arguments for these
claims beyond those that Appellants presented for claim 1. (See App. Br. 8-
17.)
Issue 2 – Claim 2
Appellants assert that the combination of Settle, Tsubouchi and
Yamauchi does not teach or suggest a counter for counting the amount of
packet header and video data and a switch for selecting the packet header or
video data, as recited in claim 2. (App. Br. 18.) Appellants argue that
because “Settle does not teach a predefined packet length, and is only
producing ‘MPEG compatible’ packets, it cannot be concluded that Settle
inherently includes a counter and switch as claimed.” (App. Br. 19.)
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Appellants’ argument is the same as one that they made for claims 1, 6, and
7. (App. Br. 9-10.) As explained above in the discussion of claim 1, the
packets disclosed in Settle have a fixed length because they are MPEG
transport packets. Because the system disclosed in Settle forms fixed-length
packets having a header and a payload of video data each of fixed length,
Settle inherently includes or renders obvious a counter, to ensure that the
packet includes the proper amount of header data and video data, and
similarly, some type of a switch to select either the header or the video data
as it is forming the packets. (See FF 3.) Therefore, we will sustain the
Examiner’s rejection of claim 2.
Issue 3 – Claim 3
In addition to repeating arguments that they had made for claims 1
and 2 and that have been addressed supra, Appellants assert that
combination of Tsubouchi, Settle and Yamauchi does not disclose “a FIFO
memory for storing the video data in response to a clock for the video data,”
as recited in claim 3. (App. Br. 20-21.) In particular, Appellants argue that
“Tsubouchi does not teach or suggest a FIFO and does not teach that the
output buffer stores data in response to a clock for the video data.” (App.
Br. 21.) As explained by the Examiner, however, Tsubouchi does, in fact,
teach a FIFO because the output buffer of Tsubouchi corresponds to the
FIFO that is recited in claim 3. (Ans. 12; accord FF 1.)
In addition, Yamauchi teaches an output buffer that stores data in
response to a clock for the video data. In particular, as explained by the
Examiner, various signals that are disclosed in Yamauchi including the clock
signal Sc1 that is derived from a horizontal synchronization signal,
correspond to the “clock” that is recited in claim 3. (Ans. 12; accord FF 5.)
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Indeed, Yamauchi’s apparatus writes the digitized video signal to memory in
accordance with signals that are derived from horizontal synchronizing
signals. Supra, pp. 10-11. Therefore, we will sustain the Examiner’s
rejection of claim 3.
Issue 4 – Claims 4 and 5
Appellants argue that claim 4 is not obvious because “the cited
Yamauchi’s teachings relate to writing data into a video memory and not to
a counter outputting a data validity signal while counting bytes of header
and video data.” (App. Br. 21-22.) In response, the Examiner notes that the
video memory write signal SW disclosed in Yamauchi “is only enabled
during the period in a particular line in a video when converted video signal
SVC corresponds to effective video data.” (Ans. 8; accord FF 6.)
As explained by the Appellants, however, “writing only valid data
into a memory location is not the same as or suggestive of generating a data
validity signal along with output video data.” (App. Br. 22.) The Examiner
fails to explain how the video memory write signal of Yamauchi renders
obvious a counter that outputs a data valid signal while counting the number
of bytes of packet header and video data, as recited in claim 4.
Therefore, we will not sustain the Examiner’s rejection of claim 4 or
claim 5, which depends from claim 4.
CONCLUSION
The Examiner did not err in finding that the combination of
Tsubouchi, Settle and Yamauchi renders obvious the limitations of a) storing
digitized video data, b) “detecting a synchronizing signal for a line of video
data,” and c) “repeating the selection of the packet header generated by said
header generation means and selection of a predetermined amount of video
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data read out of said memory as a payload” during an interval between the
detection of the synchronizing signals for one line of data and the next line
of data whereby “the selection of video data is completed during the
horizontal synchronizing period,” as recited in claim 1, and as similarly
recited in claims 6 and 7. The Examiner did not err in finding that the
combination of Tsubouchi, Settle and Yamauchi renders obvious a counter
for counting the amount of packet header and video data and a switch for
selecting the packet header or video data, as recited in claim 2. The
Examiner did not err in finding that the combination of Tsubouchi, Settle
and Yamauchi renders obvious the limitations of a) converting the format of
digitized video data “to a pseudo MPEG2-TS format” and b) “a FIFO
memory for storing the video data in response to a clock for the video data,”
as recited in claim 3.
The Examiner did err in finding that the combination of Tsubouchi,
Settle and Yamauchi renders obvious claims 4 and 5.
DECISION
We affirm the Examiner's decision rejecting claims 1-3 and 6-7 and
reverse the Examiner’s decision rejecting claims 4 and 5.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136. See 37 C.F.R.
§ 1.136(a)(1)(v) (2010).
AFFIRMED-IN-PART

ak

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Douglas W. Cameron
Intellectual Property Department
IBM Corporation
P.O. Box 218
Yorktown Heights, NY 10598