Ex Parte Krause

Patent Trial and Appeal Board

Mar 30, 2018

14009771 (P.T.A.B. Mar. 30, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
14/009,771 10/03/2013 Michael R. Krause
56436 7590 04/03/2018
Hewlett Packard Enterprise
3404 E. Harmony Road
Mail Stop 79
Fort Collins, CO 80528
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
83543637 3015
EXAMINER
OBERLY, ERIC T
ART UNIT PAPER NUMBER
2184
NOTIFICATION DATE DELIVERY MODE
04/03/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
hpe.ip.mail@hpe.com
chris.mania@hpe.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte MICHAEL R. KRAUSE
Appeal2016-005316
Application 14/009, 771 1
Technology Center 2100
Before JASON V. MORGAN, MICHAEL M. BARRY, and
PHILLIP A. BENNETT, Administrative Patent Judges.
MORGAN, Administrative Patent Judge.
DECISION ON APPEAL
1 Appellant identifies Hewlett-Packard Development Company, LP,
a wholly-owned affiliate of Hewlett-Packard Company with HPQ Holdings,
LLC, as the general or managing partner, as the real party in interest. App.
Br. 2. We note, for completeness, that, shortly after the Appeal Brief was
filed (Sept. 21, 2015) assignment to Hewlett-Packard Enterprise
Development LP was executed (Oct. 27, 2015) and recorded (Nov. 9, 2015).
Patent Assignments Reel 037079, Frame 0001.
Appeal 2016-005316
Application 14/009, 771
STATEMENT OF THE CASE
Introduction
This is an appeal under 35 U.S.C. § 134(a) from the Examiner's final
rejection of claims 1-15. This appeal is related to appeal number 2016-
005314.2 We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.
Invention
Appellant discloses "a system for processing local input/ output" that
includes an upper device with "one or more transmit/receive work queues"
2 The two appeals should have been identified as being related to each other
for a number of reasons, including, but not limited to: (1) the applications
sharing near-identical disclosures; (2) the applications both facing
provisional obviousness-type double patenting rejections based, at least in
part, on each other; (3) the applications reciting similar systems, methods,
and non-transitory computer-readable media; (4) the applications having the
same inventor and assignee; ( 5) the same legal representative filing both
Appeal Briefs; ( 6) overlapping prior art being used in the Final Office
Actions; and (7) similar issues being raised in both appeals. In addition to
these signs that the appeals were related, the Appeal Brief in this case was
filed on September 21, 2015, more than two months after the July 15, 2015,
filing of the Notice of Appeal in the related case, and only one week after
the Appeal Brief in the related case was filed (Sept. 14, 2015). Nonetheless,
the Appeal Brief asserts "Appellant is unaware of any other appeals or
interferences related to this Appeal." App. Br. 2.
Appellant and Appellant's counsel are reminded of their duty to
identify "all other prior and pending appeals, interferences, trials before the
Board, or judicial proceedings ... which satisfy all of the following
conditions: involve an application or patent owned by the appellant or
assignee, are known to appellant, the appellant's legal representative, or
assignee, and may be related to, directly affect or be directly affected by or
have a bearing on the Board's decision in the pending appeal." 37 C.F.R.
§ 41.37(c)(l)(ii) (2015).
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Application 14/009, 771
and a stateless lower device. Spec., Abstract. "Data packets passed between
the upper device and the lower include a data flow identifier used to identify
data flow resources of the upper device and the lower device corresponding
to the data packet." Id.
Representative Claim (key limitations emphasized)
1. A system for processing local input/ output,
compnsmg:
a processor coupled to a host memory through a memory
controller;
an upper device communicatively coupled to the memory
controller, the upper device comprising one or more
transmit/receive work queues;
a lower device communicatively coupled to the upper device,
wherein the lower device is stateless; and
wherein data packets passed between the upper device and the
lower device include a data flow identifier used to
identify data flow resources of the upper device and the
lower device corresponding to the data packet.
Rejections
The Examiner provisionally rejects claims 1-15 on the ground of non-
statutory obviousness-type double-patenting over co-pending applications
Krause '769, App. No. 14/009,769 (filed Oct. 3, 2013), and Krause '761,
App. No. 14/009,761 (filed Oct. 3, 2013). Final Act. 3--4. Claims 1-20 of
Krause '761 were found allowable (Notice of Allowance, May 12, 2016),
but the application was abandoned for failure to timely pay the required
issue and publication fees (Notice of Abandonment, Aug. 31, 2016).
Because the provisional rejection cited to both co-pending applications
(including the abandoned application) together, rather than to each co-
pending application as providing a separate basis for the rejection, the
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Application 14/009, 771
provisional non-statutory obviousness-type double-patenting rejection is
moot. Therefore, we deem this rejection no longer before us and, we do not
address this rejection further herein.
The Examiner rejects claims 1-3, 5, 8, 9, and 13 under 35 U.S.C.
§ 102(b) as being anticipated by Muller et al. (US 2006/0251109 Al,
published Nov. 9, 2006). Final Act. 4--7.
The Examiner rejects claim 4 under 35 U.S.C. § 103(a) as being
unpatentable over Muller and Mukherjee et al. (US 2009/0119663 Al,
published May 7, 2009). Final Act. 8-9.
The Examiner rejects claim 6 under 35 U.S.C. § 103(a) as being
unpatentable over Muller and McGee et al. (US 2007/0268820 Al,
published Nov. 22, 2007). Final Act. 9.
The Examiner rejects claim 7 under 35 U.S.C. § 103 as being
unpatentable over Muller and Gulick et al. (US 6,314,501 B 1, issued Nov. 6,
2001). Final Act. 12-13.
The Examiner rejects claims 10, 12, 14, and 15 under 35 U.S.C.
§ 103(a) as being unpatentable over Muller and Riddoch (US 2010/0161847
Al, published June 24, 2010). Final Act. 10-12.
The Examiner rejects claim 11 under 35 U.S.C. § 103(a) as being
unpatentable over Muller, Riddoch, and Aybay et al. (US 2010/0106866 Al,
published Apr. 29, 2010). Final Act. 14.
ANALYSIS
With respect to the Examiner's 35 U.S.C. §§ 102(b), 103(a)
rejections, we agree with and adopt as our own the Examiner's findings of
facts and conclusions as set forth in the Answer and in the Final Office
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Action from which this appeal was taken. We have considered Appellant's
arguments, but do not find them persuasive of error. We provide the
following explanation for emphasis.
Claims 1 and 4-15
In rejecting claim 1under35 U.S.C. § 102(b), the Examiner finds
Muller's disclosure of a network interface unit (NIU) having receive packet
first-in first-out (FIFO) queues, receive direct memory access (DMA)
channel groups, media access control (MAC) modules, and a packet
classifier module that determines to which DMA channel group a packet
belongs discloses both the claimed upper device and lower device, wherein
the lower device is stateless and wherein data packets passed between the
upper device and the lower device include a data flow identifier used to
identify data flow resources of the upper device and the lower device
corresponding to the data packet. Final Act. 4--5 (citing, e.g., Muller i-fi-1 7 5-
76, 80, 91, 185, Figs. 5A-B); see also Ans. 3-8 (citing, inter alia, Muller
i191). Specifically, the Examiner finds that Muller's media access control
modules, which provide continuous packet service, disclose that the lower
device is stateless. Final Act. 5 (citing Muller i-f 185). The Examiner also
finds that Muller's classification of packets based on packet header
information discloses the claimed use of a data flow identifier. Final Act. 5
(citing Muller i-fi-175-76, 91, Fig. 5A).
Appellant contends the Examiner erred in mapping certain
components of Muller's network interface unit to the claimed upper and
lower devices because "the terms 'upper device' and 'lower device' are
clearly defined in the specification." App. Br. 10. Appellant argues "[t]he
upper device is described as being an I/O device that is 'processor
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integrated."' Id. at 11 (citing Spec. i-f 17); see also App. Br. 13 ("selection of
a DMA channel as in Muller is the selection of a resource of the lower
device, i.e., the NIU"); Reply Br. 2 ("the NIU should be compared to the
lower device recited"). Appellant also argues "the NIU of Muller is outside
of the coherency domain and cannot be considered to manage host
resources"). Reply Br. 4. Consistent with Appellant's characterization of
Muller as failing to disclose the claimed upper and lower devices, Appellant
argues Muller's "network interface unit 110 itself includes DMA channels
and a mapping function for assigning packets to particular DMA channels
based on the packet classifier [and thus] does not read on the stateless lower
device recited." App. Br. 10; see also Reply Br. 3.
Appellant's arguments are not persuasive because we agree with the
Examiner that the claimed devices are not each "limited to a singular,
separate, or exclusive component[,] but rather [encompass] a collection of
elements which may be construed as 'upper' and 'lower' in relation to
placement and/or functionality." Ans. 3. The Examiner's interpretation of a
device (whether upper or lower) is consistent with the Specification, which
illustrates upper and lower devices as having a collection of components
(see, e.g., Spec., Fig. 1 ), but fails to define the terms upper and lower so as
to preclude the devices as being part of a larger device. Moreover, the
features Appellant identifies as distinguishing an upper device from certain
components of Muller's network interface unit are not recited in claim 1, nor
does the Specification define or describe upper device in such a manner that
it would require these features. For example, the Specification discloses an
"I/O processing system [that] may include a processor-integrated upper-I/O
device." Spec. i-f 17. However, claim 1 recites "a processor" and "an upper
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device" separately, without any recitations requiring that the upper device be
"processor-integrated" as described in the example provided in the
Specification. Moreover, the Specification merely discloses non-limiting
examples of an upper device that "handles host resource management and
error processing" when the upper device is "processor-integrated" (Spec.
i-f 1 7) or that "operates in the coherency domain of the processor" when the
processor is "configured with a coherency protocol" (id. i-f 22). Therefore,
we agree with the Examiner that the claimed upper device and lower device
encompass collections of components on Muller's network interface unit.
See Final Act. 4--5; Ans. 2-3. Appellant's arguments are also not persuasive
to the extent they are not responsive to the Examiner's rejection because
they are inconsistent with a mapping of certain components of Muller's
network interface unit to the claimed upper device and other components of
Muller's network interface unit to the claimed lower device.
Appellant further argues the Examiner erred because "continuous
packet service is not synonymous with stateless." App. Br. 11-12. In
particular, Appellant argues that statelessness is defined in the Specification
as "meaning that [the stateless lower device] does not maintain state of host-
specific processing such as IOMMU mappings and it does not maintain state
that is used by the host to continue to operate should the device fail." Id. at
11 (quoting Spec. i-f 18); see also Reply Br. 2. Appellant argues that "Muller
appears to disclose stateful Direct Memory Access (DMA) techniques," and
therefore fails to disclose a lower device that is stateless. App. Br. 12.
Appellant's arguments are unpersuasive because
the MAC/classifier/queuing layer of the NIU, which the
examiner equate[ s to] the lower device, do not have direct
access to the host memory/queues/buffers and state information
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since the MAC/classifier/queuing layer of the NIU steer the
flow of packets to the DMA controller and respective DMA
channels, which have been equated in part to the "upper
device."
Ans. 4; see also Final Act. 5; Muller, Fig. 5A, i-f 91. We are unable to
discern any disclosures in Muller showing that the components identified by
the Examiner as being part of Muller's lower device maintain any host-
specific state information. We note that the flow table of Muller (see i-f 75)
does not represent the maintenance of proscribed state information because
claim 2, which depends from claim 1, explicitly recites that "the lower
device includes a data flow lookup table." Moreover, the teaching in the
prior art reference need not be ipsissimis verbis (i.e., Muller does not need to
explicitly identify its lower device components as being stateless).
Structural Rubber Products v. Park Rubber, 749 F.2d 707, 716 (Fed. Cir.
1984). Therefore, we agree with the Examiner that Muller discloses
"wherein the lower device is stateless," as recited in claim 1.
Appellant also contends the Examiner erred because "Muller's packet
classifier is used, in conjunction with a flow table, to classify data packets
based on packet header information and then assign[ s] the data packets to
particular DMA channels." App. Br. 12 (citing Muller i-fi-175-79, Fig. 5A).
Appellant argues "the packet header information is an address in the
memory system for the DMA channel to which a data packet is sent." Reply
Br. 4--5. Thus, Appellant argues Muller fails to disclose wherein data
packets passed between the upper device and the lower device include a
data flow identifier used to identify data flow resources of the upper device
and the lower device corresponding to the data packet. App. Br. 12.
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Appellant does not persuasively distinguish the claimed data flow
identifier from Muller's "'packet header information[,]' which is used to
classify the packet." Ans. 7 (citing Muller i-f 91 ). Appellant's contention
that because the "the classifier uses packet header information to 'steer' the
data packet to the appropriate DMA channel" and "DMA channels are
allocated as ring buffers in the memory system," therefore, "the packet
header information is an address in the memory system for the DMA
channel to which a data packet is sent" is unpersuasive. Reply Br. 4--5
(citing Muller i-fi-175, 91, 129). However, we agree with the Examiner that
the DMA channel selection in Muller is directed to the use of packet header
information to identify a resource (i.e., one of the network interface unit's
receive DMA channels) of the upper device corresponding to the data
packet. See, e.g., Muller, Fig. 5A. In particular, we agree with the Examiner
that the DMA channels of Muller's network interface unit are data flow
resources of the upper device. Id. The claimed invention does not preclude
an upper device data flow resource from encompassing ring buffers
allocated in a memory system. The portion of Muller's network interface
unit the Examiner maps to the claimed lower device passes data to the upper
device through the first-in, first-out queues, which is consistent with
Appellant's preferred embodiment in which the data flow identifier "is not
used by the lower device to directly access host memory" but instead "can
be used by the upper device to identify a corresponding physical memory
address associated with the data flow identifier." Spec. i-f 36 (reference
numbers omitted). Therefore, we agree with the Examiner that Muller
discloses "wherein data packets passed between the upper device and the
lower device include a data flow identifier used to identify data flow
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resources of the upper device and the lower device corresponding to the data
packet," as recited in claim 1.
Accordingly, we sustain the Examiner's 35 U.S.C. § 102(b) rejection
of claim 1, and claims 5, 8, 9, and 13, which Appellant does not argue
separately. App. Br. 13. Appellant's arguments with respect to claims 4, 6,
7, 10-12, 14, and 15 are either conclusory or limited to the contention that
other prior art relied on by the Examiner fails to cure alleged deficiencies of
Muller. See id. at 15-19. As detailed above, Muller is not deficient.
Accordingly, we sustain the Examiner's 35 U.S.C. § 103(a) rejections of
these claims.
Claims 2 and 3
Appellant contends the Examiner erred in rejecting claim 2 under
35 U.S.C. § 103(a) because "Muller clearly fails to disclose that the lower
device includes a data flow lookup table including the data flow identifiers."
App. Br. 14. Specifically, Appellant argues the claimed "lower device
contains a data flow lookup table that includes data flow identifiers for the
data flow resources of another device. In contrast, Muller's flow table does
not include data flow identifiers for the data flow resources of a different
device." Id. However, for the reasons discussed above, we agree with the
Examiner that "the DMA channels [of Muller] pertain to the equated 'upper
device' and represent 'data flow resources of a different device' in relation
to the features of Muller applied against the claimed 'lower device."' Ans.
9. Appellant's arguments, therefore, are unpersuasive.
Accordingly, we sustain the Examiner's 35 U.S.C. § 102(b) rejection
of claim 2, and claim 3, which Appellant does not argue separately.
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DECISION
We affirm the Examiner's decision rejecting claims 1-15.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 41.50(±).
AFFIRMED
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