Ex Parte Kohn et al

Board of Patent Appeals and Interferences

Apr 16, 2012

10273829 (B.P.A.I. Apr. 16, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/273,829 10/17/2002 Leslie D. Kohn SUNMP126 3919
32291 7590 04/17/2012
MARTINE PENILLA GROUP, LLP
710 LAKEWAY DRIVE
SUITE 200
SUNNYVALE, CA 94085
EXAMINER
CLEARY, THOMAS J
ART UNIT PAPER NUMBER
2111
MAIL DATE DELIVERY MODE
04/17/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________
BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________
Ex parte LESLIE D. KOHN and MICHAEL K. WONG
____________
Appeal 2010-000805
Application 10/273,829
Technology Center 2100
____________

Before ROBERT E. NAPPI, KALYAN K. DESHPANDE, and
MICHAEL R. ZECHER, Administrative Patent Judges.

ZECHER, Administrative Patent Judge.

DECISION ON APPEAL
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I. STATEMENT OF THE CASE
Appellants appeals under 35 U.S.C. § 134(a) (2002) from the
Examiner’s Final Rejection of claims 1-3, 5, 6, 8, 10, 11, 13, 15, and 16. Br.
3. Claims 4, 7, 9, 12, 14, and 17-19 have been cancelled. Claims App’x;
Ans. 2. We have jurisdiction under 35 U.S.C. § 6(b) (2008).
We affirm.
Appellants’ Invention
Appellants invented an apparatus and method for caching dynamic
random-access memory to reduce the bandwidth usage between a processor
and a memory system interface. See Spec. ¶ [11].
Illustrative Claim
1. A server comprising:
a processor;
a memory system;
a network interface included in a same die as the
processor;
a bus system including a peripheral bus coupling the
memory system to the processor;
a data switch included in the same die as the processor,
the data switch being coupled to the peripheral bus;
an egress buffer, the egress buffer being separate from
the memory system;
a first dedicated bus coupling the processor to the data
switch;
a second dedicated bus coupling the network interface to
the data switch; and
an egress bus providing a dedicated connection from the
data switch to the egress buffer, the egress bus being separate
from the peripheral bus, the egress bus being a parallel bus, the
egress buffer and the egress bus have a data throughput rate that
is greater than or equal to about twice the amount of a data
stream to be served, the data switch operative to selectively
direct unprocessed data from the memory system to the
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processor, the data switch also operative to selectively direct
processed data flow from the processor to the egress buffer or
the memory system, the data switch also operative to
selectively direct processed data flow from the egress bus to the
network interface or from the processor to the network
interface, wherein the processed data includes at least one of
encrypted or decrypted data.

Prior Art Relied Upon
Tjandrasuwita US 5,422,654 June 6, 1995
Mori US 5,838,603 Nov. 17, 1998
Schnell US 5,923,654 July 13, 1999
Chin US 6,216,205 B1 Apr. 10, 2001
Vairavan US 2002/0083344 A1 June 27, 2002
(filed June 27, 2001)
Badamo US 2002/0184487 A1 Dec. 5, 2002
(filed Mar. 23, 2001)
Pham US 2003/0074388 A1 Apr. 17, 2003
(filed Oct. 12, 2001)

FREE ON-LINE DICTIONAY OF COMPUTING, FOLDOC, (1995-1999)
(search terms: word, double data rate random access memory),
http://foldoc.org/ (“FOLDOC”).

Daniel Rutter, “OCZ Technology PC3200 Revision 2 DDR RAM,”
(Aug. 2002) retrieved from
http://www.web.archive.org/web/20020827115212/http://www.dansdata.co
m/oczpc3200.htm (last visited Mar. 1, 2005) (“Rutter”).

Rejections on Appeal
Claims 1-3, 10, 11, 13, and 15 stand rejected under 35 U.S.C. § 103(a)
as being unpatentable over the combination of Schnell, Mori, Tjandrasuwita,
FOLDOC, and the knowledge commonly known in the art as evidenced by
Pham, Badamo, and Vairavan. Ans. 4-8.
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Claims 5, 6, and 8 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Schnell, Mori, Tjandrasuwita,
FOLDOC, Rutter, and the knowledge commonly known in the art as
evidenced by Pham, Badamo, and Vairavan. Ans. 8-9.
Claim 16 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Schnell, Mori, Tjandrasuwita,
FOLDOC, Chin, and the knowledge commonly known in the art as
evidenced by Pham, Badamo, and Vairavan. Ans. 9-10.

II. OPINION
Appellants contend on pages 6-9 of the Brief that the Examiner
erroneously rejects independent claim 1. These contentions present us with
the following issues: did the Examiner err in finding that the combination of
Schnell, Mori, Tjandrasuwita, FOLDOC, and the knowledge commonly
known in the art as evidenced by Pham, Badamo, and Vairavan teaches or
suggests the following claim limitations recited in independent claim 1:
(a) “a processor;”
(b) “the data switch being coupled to the peripheral bus;”
(c) “an egress buffer, the egress buffer being separate from the
memory system;”
(d) “a first dedicated bus coupling the processor to the data
switch;”
(e) “a second dedicated bus coupling the network interface to the
data switch;” and
(f) “an egress bus providing a dedicated connection from the data
switch to the egress buffer . . .”?
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III. ANALYSIS
Claim 1
We have reviewed the Examiner’s obviousness rejection in light of
Appellants’ contentions that the Examiner has erred. We do not find error in
the Examiner’s obviousness rejection of independent claim 1, which recites,
inter alia:
[1)] a processor; [2)] the data switch being coupled to the
peripheral bus; [3)] an egress buffer, the egress buffer being
separate from the memory system; [4)] a first dedicated bus
coupling the processor to the data switch; [5)] a second
dedicated bus coupling the network interface to the data switch;
and [6)] an egress bus providing a dedicated connection from
the data switch to the egress buffer. . . .

Rather than address the disputed claim limitations based on the order
recited in independent claim 1, we will address Appellants’ contentions
based on the order set forth in the Brief. First, Appellants contend that the
Schnell’s IBUF0 and OBUF1 do not teach or suggest the claimed “egress
bus.” Br. 6. The Examiner finds that Schnell’s IBUF1 and OBUF1 teach or
suggest “an egress bus providing a dedicated connection from the data
switch to the egress buffer,” as claimed. Ans. 10. We agree with the
Examiner. In particular, since Schnell’s IBUF1 and OBUF1 transmit data
packets between the switch matrix and BUFFER1 (col. 6, ll. 31-36), we find
that such channels provide a dedicated connection for data throughput—
thereby amounting to the claimed “egress bus.” Second, Appellants contend
that the Schnell’s BUFFER1 does not teach or suggest the claimed “egress
buffer.” Br. 6. The Examiner that finds that since Schnell’s BUFFER1
receives data packets via channels IBUF1 and OBUF1 (id), and is separate
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and distinct from BUFFER2 (see figure 2)—otherwise known as the claimed
“memory system”—Schnell’s BUFFER1 teaches or suggests the “egress
buffer, the egress buffer being separate from the memory system,” as
claimed. Ans. 11. We agree with the Examiner.
Third, we are not persuaded by Appellants’ argument that the cited
prior art references provide a comprehensive teaching that is contrary to the
objectives of the claimed invention—namely adding dedicated buses,
increasing size and pin count to gain speed. Br. 7. We note that Appellants’
argument is not commensurate in scope with the claim limitations explicitly
recited in independent claim 1. Moreover, Appellants fail to provide any
textual portions of the cited prior art references that contradict the objectives
of the claimed invention.
Fourth, we are not persuaded by Appellants’ argument that Schnell’s
network switch does not teach or suggest a server capable of performing
multiple functions. Br. 7. We note that “[a] server” is only recited in the
preamble of independent claim 1. In general, a preamble is construed as a
limitation “if it recites essential structure or steps, or if it is ‘necessary to
give life, meaning, and vitality’ to the claim.” Catalina Mktg. Int'l, Inc. v.
Coolsavings.com, Inc., 289 F.3d 801, 808 (Fed. Cir. 2002) (quoting Pitney
Bowes, Inc. v. Hewlett-Packard Co., 182 F.3d 1298, 1305 (Fed. Cir. 1999)).
A preamble is not limiting, however, “‘where a patentee defines a
structurally complete invention in the claim body and uses the preamble only
to state a purpose or intended use for the invention.”’ Id. (quoting Rowe v.
Dror, 112 F.3d 473, 478 (Fed. Cir. 1997)); see also Symantec Corp. v.
Computer Assocs. Int'l Inc., 522 F.3d 1279, 1288 (Fed. Cir. 2008).
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In this case, we find that Appellants have defined a structurally
complete apparatus or machine comprising, inter alia, “a processor,” “a
memory system,” “ a bus system,” and “a data switch.” Consequently, we
find that the nominal recitation of “[a] server” in the preamble amounts to a
mere statement of intended use and, therefore, should not be entitled to any
patentable weight because it does not breathe life into the body of
independent claim 1. Moreover, contrary to Appellants’ argument,
Schnell’s network switch is capable of performing multiple functions,
including the same function of processing data (col. 6, ll. 9-13) as the
claimed invention. Put another way, we find that Schnell’s network switch
amounts to a server because it is capable of performing multiple functions,
including processing data.
Fifth, we are not persuaded by Appellants’ argument that Schnell’s
IBUF1 and 0BUF1 are not the same as the claimed “egress bus,” due in part
to the difference in connections—Schnell’s input switch is not coupled to
processor, nor does such switch transfer data to or from the processor, as
claimed. Br. 7-8. In light of our analysis supra, we agree with the Examiner
that Schnell’s IBUF1 and OBUF1 teach or suggest the claimed “egress bus.”
Moreover, we agree with the Examiner that Schnell’s IBUF1 couples the
input switch contained within the switch matrix to BUFFER1, and Schnell’s
OBUF1 couples the output switch of the switch matrix to BUFFER1 (see
figure 2). Ans. 13. We find that such channels provide the same dedicated
connection as the claimed “egress bus.” Further, since Schnell’s switch
matrix indirectly couples IBUF1 and OBUF1 to the packet and management
processors (col. 6, l. 31-col. 7, l. 22), we find that Schnell teaches or
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suggests “the data switch being coupled to the peripheral bus [included in
the bus system],” as recited in independent claim 1.
Sixth, Appellants’ contend that Schnell’s packet and management
processors do not teach or suggest the claimed “processor” because the
packet and management processors are not for processing data, but rather
only serve as internal controls for the network switch. Br. 8. The Examiner
finds that Schnell’s packet processor, which receives a packet from the
switch network, determines the appropriate action for such packet, and re-
submits the packet to the switch network for routing to one of the IOPORTs
(col. 10, ll. 20-23), teaches or suggests the claimed “processor.” Ans. 11-12.
We agree with the Examiner. In particular, we note that Schnell’s packet
processor not only serves as an internal control for the network switch (see
figure 2), but is also capable of performing the same function as the claimed
invention—namely processing data packets (col. 10, ll. 20-23).
Seventh, we are not persuaded by Appellants’ arguments that: 1)
Schnell does not teach or suggest different types of buffers where some
buffers are coupled to a processor via a dedicated bus and other buffers are
coupled to a processor via a multipurpose bus; and 2) none of Shell’s
BUFFER1, OBUF1 or IBUF1 are coupled to the processor, as claimed. Br.
8. We note that the only buffer recited in independent claim 1 is the “egress
buffer” and, in light of our discussion supra, we agree with the Examiner
that Schnell’s BUFFER1 teaches or suggests the claimed “egress buffer.”
Further, Appellants fail to explicit state which of the two “dedicated bus[es]”
the Examiner erroneously rejects. Nonetheless, we agree with the Examiner
that Schnell’s RXDATA25 and TXDATA25 amount to a dedicated bus that
is capable of transmitting data between the packet processor and the switch
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matrix (col. 6, ll. 60-63; figure 2). See Ans. 5 and 15-16. Consequently, we
find that Schnell teaches or suggests “a first dedicated bus coupling the
processor to the data switch,” as recited in independent claim 1. Moreover,
we agree with the Examiner that Schnell’s RXDATA2 and TXDATA2
amount to a dedicated bus that is capable of transmitting data between the
IOPORT2 and the switch matric (col. 6, ll. 13-20; figure 2). Ans. 5 and 16.
As such, we find that Schnell teaches or suggests “a second dedicated bus
coupling the network interface to the data switch,” as recited in independent
claim 1.
Finally, we are not persuaded by Appellants’ arguments that: 1) none
of the cited references teach or suggest a data switch coupled in the manner
set forth in independent claim 1, combined with processing data and not
simply buffering the data; and 2) none of the cited prior art references,
whether considered individually or in any combination, teach or suggest the
switch directly processes data flow from the processor, through the switch to
the egress buffer and also from the egress buffer to the network interface, via
multiple dedicated buses and thereby enabling the processor to store the
processed data in the egress buffer at the same time the egress buffer outputs
processed data to the network interface. Br. 9.
Appellants’ arguments amount to no more than reciting the claim
features and generally alleging that the cited prior art references are
deficient. Merely pointing out certain claim features recited in independent
claim 1 and nakedly asserting that none of the cited prior art references teach
or suggest such features does not amount to a separate patentability
argument. See 37 C.F.R. § 41.37(c)(vii) (“A statement which merely points
out what a claim recites will not be considered an argument for separate
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patentability of the claim.”); see also In re Lovin, 652 F.3d 1349, 1357 (Fed.
Cir. 2011) (“[W]e hold that the Board reasonably interpreted Rule 41.37 to
require more substantive arguments in an appeal brief than a mere recitation
of the claim elements and a naked assertion that the corresponding elements
were not found in the prior art.”); cf. In re Baxter Travenol Labs., 952 F.2d
388, 391 (Fed. Cir. 1991) (“It is not the function of this court to examine the
claims in greater detail than argued by an appellant, looking for [patentable]
distinctions over the prior art.”). It follows that the Examiner has not erred
in concluding that the combination of Schnell, Mori, Tjandrasuwita,
FOLDOC, and the knowledge commonly known in the art as evidenced by
Pham, Badamo, and Vairavan renders independent claim 1 unpatentable.
Claims 2, 3, 5, 6, 8, and 10
Appellants do not provide separate and distinct arguments for
patentability with respect to dependent claims 2, 3, 5, 6, 8, and 10. See Br.
6-9. Therefore, since Appellants group dependent claims 2, 3, 5, 6, 8, and
10 with independent claim 1 (see Br. 9 and 11), these claims fall with
independent claim 1. See 37 C.F.R. § 41.37(c)(l)(vii).
Claim 11
Appellants offer the same argument set forth in response to the
obviousness rejection of independent claim 1 to rebut the obviousness
rejection of independent claim 11. See Br. 9-11. We have already addressed
these arguments in our discussion of independent claim 1, and we found
them unpersuasive. It follows that the Examiner has not erred in concluding
that the combination of Schnell, Mori, Tjandrasuwita, FOLDOC, and the
knowledge commonly known in the art as evidenced by Pham, Badamo, and
Vairavan renders in independent claim 11 unpatentable.
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Claim 13, 15, and 16
Appellants do not provide separate and distinct arguments for
patentability with respect to dependent claims 13, 15, and 16. See Br. 9-11.
Therefore, since Appellants group dependent claims 13, 15, and 16 with
independent claim 11 (see Br. 10-11), these claims fall with independent
claim 11. See 37 C.F.R. § 41.37(c)(l)(vii).

IV. CONCLUSION
The Examiner has not erred in rejecting claims 1-3, 5, 6, 8, 10, 11, 13,
15, and 16 as being unpatentable under 35 U.S.C. § 103(a).

V. DECISION
We affirm the Examiner’s decision to reject claims 1-3, 5, 6, 8, 10, 11,
13, 15, and 16.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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