Ex Parte Kohn

Patent Trial and Appeal Board

Feb 27, 2013

10273718 (P.T.A.B. Feb. 27, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/273,718 10/18/2002 Leslie D. Kohn SUNMP128 3695
32291 7590 02/28/2013
MARTINE PENILLA GROUP, LLP
710 LAKEWAY DRIVE
SUITE 200
SUNNYVALE, CA 94085
EXAMINER
YALEW, FIKREMARIAM A
ART UNIT PAPER NUMBER
2436
MAIL DATE DELIVERY MODE
02/28/2013 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte LESLIE D. KOHN
____________

Appeal 2010-007971
Application 10/273,718
Technology Center 2400
____________

Before SCOTT R. BOALICK, BARBARA A. BENOIT, and
JAMES B. ARPIN, Administrative Patent Judges.

BENOIT, Administrative Patent Judge.

DECISION ON APPEAL
This is an appeal under 35 U.S.C. § 134(a) from the final rejection of
claims 1, 4-9, and 11-19, which constitute all the claims pending in the
application. Claims 2, 3, 10, and 20 have been canceled. App. Br. 3. We
have jurisdiction under 35 U.S.C. § 6(b). We affirm.

Appeal 2010-007971
Application 10/273,718

2
STATEMENT OF THE CASE
Appellant’s invention relates to a microprocessor that includes a
cryptographic co-processor within the microprocessor die. See generally
Abstract; Spec. ¶ 2. Claim 1 is illustrative and reads as follows, with key
disputed limitations emphasized:
1. A microprocessor comprising:
a first processing core consisting of:
an instruction decode unit;
an instruction execution unit; and
a load/store unit; and
a first cryptographic co-processor located on a first die with the first
processing core, the first cryptographic co-processor operable to perform a
plurality of encryption and decryption operations for encrypted data
transactions the cryptographic coprocessor including an integer multiplier
unit that is coupled to the instruction execution unit and the first
cryptographic co-processor, wherein the integer multiplier unit being
directly accessible by both the first cryptographic co-processor and by the
first processing core, wherein the integer multiplier unit is the only integer
multiplier unit directly accessible by the first processing core and wherein
the integer multiplier unit is shared by the first processing core and the first
cryptographic co-processor.
The Examiner relies on the following as evidence of unpatentability:
Petrick US 5,892,966 Apr. 6, 1999
Davis US 6,209,098 B1 Mar. 27, 2001
Callum US 2002/0027988 A1 Mar. 7, 2002
(filed Aug. 14, 2001)
The Rejections
1. The Examiner rejected claims 1, 4, 5, 9, and 11-19 under 35 U.S.C.
§ 103(a) as unpatentable over Callum and Petrick. Ans. 3-6.
2. The Examiner rejected claims 6-8 under 35 U.S.C. § 103(a) as
unpatentable over Callum, Petrick, and Davis. Ans. 6-7.
Appeal 2010-007971
Application 10/273,718

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THE OBVIOUSNESS REJECTION OVER CALLUM AND PETRICK
The Examiner finds that Callum substantially teaches or suggests all
of the limitations of illustrative claim 1, including a first cryptographic co-
processor located on a first die with the first processing core. Ans. 3 (citing
¶ 0020; Fig. 2 (step 110), as teaching the first cryptographic co-processor
located on a first die with the first processing core). The Examiner finds,
however, that Callum does not explicitly teach or suggest a first processing
core consisting of an instruction decode unit, an instruction execution unit,
and a load/store unit, but that Petrick teaches these limitations. Ans. 3.
Further, the Examiner finds that it would have been obvious to modify
Petrick’s first processing core with Callum’s apparatus to improve the
performance of the microprocessor. Ans. 4.
First, Appellant argues Callum’s cryptographic accelerator is not a
processor. App. Br. 6-7. Rather, according to Appellant, Callum’s
cryptographic accelerator is a mere rearrangement of signal lines and cannot
perform encryption and decryption processes. App. Br. 7.
We are not persuaded. We agree with the Examiner that Callum
discloses the “cryptographic co-processor located on a first die with the first
processing core,” as recited in claim 1 (Ans. 3). In a portion cited by the
Examiner, Callum teaches a processor including an arithmetic logic unit that
includes a hardware cryptographic accelerator that discloses core rearranges
bit representations of incoming information 240 to produce outgoing
information 250 in accordance with a selected cryptographic function. See
Callum, ¶ 0020.
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Appellant has not provided a persuasive explanation why the
embodiment of Callum’s cryptographic accelerator 230 hardware in Figure
2, which rearranges incoming data to produce outgoing information in
accordance with a selected cryptographic function, is not a processor. Mere
speculation unsupported by factual evidence is entitled to little probative
weight. Cf. In re Geisler, 116 F.3d 1465, 1470 (Fed. Cir. 1997). Moreover,
Appellant’s argument (App. Br. 6-7) regarding the limitation of Callum’s
cryptographic accelerator 230 to a series of buses and selector lines is based
on Callum’s embodiment in Figure 3, which is not the embodiment to which
the Examiner points (Ans. 3 (citing Fig. 2)), and so is unavailing.
Appellant’s argument that Callum’s cryptographic accelerator is not a
processor as defined by Callum (App. Br. 6-7) is not germane to the
rejection. Identity of terminology between an applied reference and a
claimed limitation is not required. Cf. In re Bond, 910 F.2d 831, 832-33
(Fed. Cir. 1990) (indicating that anticipation does not require an ipsissimis
verbis test). Moreover, we do not agree with Appellant’s assertion that
Callum’s cryptographic accelerator is not a processor, as that term is
described by Callum (App. Br. 6-7). Callum describes processor as
“includ[ing] any device having processing capability such as, for example, a
general purpose microprocessor, a microcontroller, a state machine and the
like.” Callum, ¶ 0017; see also App. Br. 6 (quoting same). As noted above,
Callum’s cryptographic accelerator is hardware that rearranges incoming
data to produce outgoing information in accordance with a selected
cryptographic function and, thus, is a device having processing capability
(i.e., the rearrangement), which is a processor according to Callum.
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Application 10/273,718

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Second, Appellant argues that Petrick does not teach or suggest that
the hardware processor and the co-processor share a single integer multiplier
unit. App. Br. 8. Rather, Appellant argues, Petrick teaches that the single
integer multiplier unit is part of the co-processor and not Petrick’s hardware
processor. Id. Appellant also contends that Petrick’s processors 200 and
202 are two distinct processors and so are not the same as the recited first
processor core and the cryptographic co-processor of claim 1. App. Br. 8-9.
Appellant’s arguments are unavailing because the Examiner relies on
the combination of Callum and Petrick for teaching “the integer multiplier
unit is shared by the first processing core and the first cryptographic co-
processor” recited in claim 1. Ans. 3-4, 8. The Examiner, for instance,
relies on Callum as teaching the first cryptographic co-processor located on
a first die with the first processing core and only relies on Petrick for
explicitly teaching a first processing core consisting of an instruction decode
unit; an instruction execution unit; and a load/store unit. Ans. 3. One cannot
show nonobviousness by attacking references individually where the
rejections are based on combinations of references. See In re Keller, 642
F.2d 413, 426 (CCPA 1981); In re Merck & Co., Inc., 800 F.2d 1091, 1097
(Fed. Cir. 1986).
Third, Appellant argues that the Examiner erred in rejecting claim 1
because the Examiner purportedly “admits that the prior art does not teach
[Appellant’s] claimed arrangement of the parts of the processor core and
crypto[graphic] co-processor.” App. Br. 12 (citing In re Japikse, 181 F.2d
1019 (CCPA 1950)) (emphasis omitted); see also App. Br. 9-12 (contending
the Examiner agreed with Appellant’s argument that Japikse supports
patentability).
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Application 10/273,718

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Appellant is correct that the Examiner no longer cites Japikse in
rejecting claim 1 as unpatentable. See generally Ans. 3-8; see also Final
Rej. (mailed July 9, 2008) 4. Appellant is incorrect, however, in indicating
that the Examiner agreed with Appellant’s argument that Japikse supports
patentability or that the prior art does not teach the arrangement of the
processor core and the cryptographic co-processor recited in claim 1.
Rather, the Examiner maintains the rejection and has submitted an
Examiner’s Answer relying on Callum and Petrick as disclosing the
arrangement of the processor core and the cryptographic co-processor, as
recited in claim 1. See Ans. 3-4, 7-8; see also Final Rej. 4 (stating “[t]he
examiner maintains the previous office action as final and withdraws the
previous cites [to] In re Japikse”). Thus, we find Appellant’s argument
unpersuasive.
Appellant contends that Japikse supports patentability of claim 1
because claim 1 requires an “integer multiplier unit that is no longer
integrated into the processor core but is instead nearby, in the
crypto[graphic]-coprocessor on the same die” and so improves the
performance of cryptographic processes. App. Br. 11-12 (emphasis added).
Appellant’s contention is not commensurate with the scope of the claim
because claim 1 does not recite that the integer multiplier unit is “in” the
cryptographic co-processor. Rather, claim 1 requires that an integer
multiplier unit (i) is coupled to the instruction execution unit and the first
cryptographic co-processor, (ii) is directly accessible by both the first
cryptographic co-processor and by the first processing core, (iii) is the only
integer multiplier unit directly accessible by the first processing core, and
(iv) is shared by the first processing core and the first cryptographic co-
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processor. Further, as noted by the Examiner in response to Appellant’s
argument, these limitations are taught by the combination of Callum and
Petrick. Ans. 8 (citing Callum, ¶¶ 0012, 0020; Fig. 2, steps 110, 200); see
also Ans. 4 (citing Callum, ¶¶ 0016, 0020; Fig. 2, steps 110, 200, 230).
Accordingly, we are not persuaded by Appellant’s argument.
Finally, Appellant argues that Petrick teaches away from the
Examiner’s proposed combination of Callum and Petrick because Petrick
teaches two distinct processors that each operate independently without
requiring access to the other processor. App. Br. 8-9. The question before
us is whether a person of ordinary skill, upon reading Petrick’s disclosure,
would be discouraged from using a first processing core consisting of an
instruction decode unit, an instruction execution unit, and a load/store unit,
as disclosed in Petrick, with the first cryptographic co-processor located on a
first die with the first processing core shown in Callum’s Figure 2. See In re
Kahn, 441 F.3d 977, 990 (Fed. Cir. 2006).
We do not agree that Petrick’s independently operating processors
would discourage an ordinarily skilled artisan from combining the
references, as determined by the Examiner. The Examiner uses Petrick for
the limited purpose of explicitly teaching a first processing core consisting
of an instruction decode unit, an instruction execution unit, and a load/store
unit (Ans. 4). As discussed above, Callum discloses two processors –
namely, the first processing core and the cryptographic accelerator 230, as
the Examiner finds (Ans. 4). Appellant has not persuaded us that Petrick
criticizes, discredits, or otherwise discourages investigation into the
invention claimed. See DePuy Spine, Inc. v. Medtronic Sofamor Danek,
Inc., 567 F.3d 1314, 1326-27 (Fed. Cir. 2009).
Appeal 2010-007971
Application 10/273,718

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To the extent that Appellant argues that the references cannot be
bodily combined because Petrick discloses independently operating
processors, such an argument is unavailing. Bodily incorporation is not
necessary in an obviousness rejection. See Keller, 642 F.2d at 425.
Thus, we agree that the Examiner’s proposed combination of Callum
and Petrick predictably uses prior art elements according to their established
functions—an obvious improvement. KSR Int’l Co. v. Teleflex Inc., 550
U.S. 398, 417 (2007). Accordingly, we find the Examiner’s reason to
combine the teachings of the cited references supported by articulated
reasoning with some rational underpinning to justify the Examiner’s
obviousness conclusion.
We are not persuaded of Examiner error, and, accordingly, we sustain
the Examiner’s rejection of (1) independent claim 1, (2) independent claim
15, and (3) dependent claims 4, 5, 9, 11-14, and 16-19, not argued separately
with particularity.

THE OBVIOUSNESS REJECTION OVER
CALLUM, PETRICK, AND DAVIS
For the rejection of claims 6-8, Appellant refers to the previous
arguments regarding claim 1. See App. Br. 14. The issues before us, then,
are the same as those presented in connection with claim 1, discussed above.
For the reasons explained above, Appellant has not persuaded us of error in
the rejections of claims 6-8.

Appeal 2010-007971
Application 10/273,718

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CONCLUSION
The Examiner did not err in rejecting claims 1, 4, 5, 9, and 11-19
under § 103 over Callum and Petrick or in rejecting claims 6-8 under § 103
as unpatentable over Callum, Petrick, and Davis.

ORDER
The Examiner’s decision rejecting claims 1, 4-9, and 11-19 is
affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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