Ex Parte Kocher et al

Patent Trial and Appeal Board

Sep 7, 2016

11387401 (P.T.A.B. Sep. 7, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
111387,401 03/23/2006
15695 7590 09/09/2016
Rambus/Finnegan
901 New York Ave., NW
Washington, DC 20001
FIRST NAMED INVENTOR
Paul C. Kocher
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
10314.0051-03000 7230
EXAMINER
DEBNATH, SUMAN
ART UNIT PAPER NUMBER
2495
NOTIFICATION DATE DELIVERY MODE
09/09/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
regional-desk@finnegan.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte PAUL C. KOCHER,
BENJAMIN C. JUN, and JOSHUA M. JAFFE
Appeal2015-005931
Application 11/387,401
Technology Center 2400
Before DEBRA K. STEPHENS, KEVIN C. TROCK, and
AARON W. MOORE, Administrative Patent Judges.
MOORE, Administrative Patent Judge.
DECISION ON APPEAL
Appeal2015-005931
Application 11/387,401
STATEMENT OF THE CASE
Appellants 1 appeal under 35 U.S.C. § 134(a) from a Final Rejection of
claims 1-19. We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.
THE INVENTION
The application is directed to "obfuscated circuits, including methods
for designing such circuits, for cryptographic authentication and other
purposes." (Spec. 1:12-13.) Claim 1, reproduced below, is illustrative:
1. A circuit configured to cryptographically authenticate itself,
compnsmg:
(a) a first plurality of logic cells selected from a first set of
supported logic cells;
(b) a second plurality of logic cells selected from a second set
of supported logic cells;
( c) a plurality of interconnections comprising conductive
elements, each interconnecting an output of a logic cell in said
first plurality of logic cells with an input of at least one logic cell
in said second plurality of logic cells, where said
interconnections between said first plurality of logic cells and
said second plurality of logic cells are selected using a random
number source, and where said interconnection selections are
configured to comply with
(i) wiring limitations, and
(ii) circuit area constraints;
( d) logic configured to receive inputs to said circuit, use said
interconnected first plurality of logic cells and said second
plurality of logic cells to cryptographically transform said inputs
1 Appellants identify Cryptography Research, Inc. as the real party in
interest. (See App. Br. 1.)
2
Appeal2015-005931
Application 11/387,401
into result values usable by an external device to authenticate
said circuit, and output said result values.
THE REJECTIONS2
Claims 1, 12, and 16 stand rejected under 35 U.S.C. § 112, first
paragraph, as failing to comply with the enablement requirement. (See Final
Act. 2-3; Ans. 2-8.)
ANALYSIS
As framed by the Examiner, "[ t ]he key question is whether there is
sufficient information available to the one skilled in [the] art to make and
use the claim, particularly [the] feature of: ' [ w ]here said interconnection
between said first plurality of logic cells and said secondary plurality of
logic cells are selected using a random number source.'" (Ans. 3.) We
conclude the Examiner has not shown3 that Appellants failed to provide an
enabling disclosure of the random selection of interconnections.
Pages 20-22 of the Specification describe "one embodiment of a
pseudoasymmetric function generator (P AFG)" that "us[ es] data from a
random number source, such as a true random number generator, a
pseudorandom number generator (such as a stream cipher), a pre-computed
2 A rejection of claims 1-19 under 35 U.S.C. § 103(a) as unpatentable over
Shona (US 6,299,069 Bl; issued Oct. 9, 2001) and Tadokoro et al. (US
6,080,206; issued June 27, 2000) has been withdrawn. (See Ans. 2.)
3 "[T]he PTO bears an initial burden of setting forth a reasonable
explanation as to why it believes that the scope of protection provided by [a]
claim is not adequately enabled by the description of the invention provided
in the specification." In re Wright, 999 F.2d 1557, 1561-62 (Fed. Cir. 1993).
3
Appeal2015-005931
Application 11/387,401
randomized input file, etc." The P AFG employs a shift register with bits
U1-U127, a key with bits Ko-K127, and a counter with bits Co-C1s. "The
computation circuit includes a series of sixty-four NAND gates 820 having
inputs Vo through V127" where "[f]or each NAND gate, the PAFG uses its
random source to randomly select one input bit from U 1 though U 127 and to
randomly select the other input bit from among Co ... C1s, Ko ... Ki27, and
U1 ... U127." (Spec. 20:21-23.) The output of the NAND gates, Wo-W63,
are inputs to a series of XOR gates, where W o-W 63 are "connected to one or
more of Xo-X127" and the remaining inputs to the XOR gates are "connected
to randomly-selected bits from Co ... C1s, Ko ... Ki27, and U1 ... U127."
(Id. at 20:25-27.) The XOR outputs are inputs to a second set ofNAND
gates, the outputs of which are the inputs to another set of XOR gates. (Id.
at 20:27-33.) The Specification explains that "[t]he output of the PAFG can
have any form, but is typically a circuit representation that can be included
directly in an application-specific integrated circuit (ASIC)." (Id. at 21 :32-
33.) Essentially, the PAFG designs an encryption circuit by creating
connections between bits and logic gates using a random number source and
then outputs the circuit design in a conventional format for production of a
physical device.
The Examiner's findings appear to be based on the notion that a set of
physical interconnections exists and a random number is somehow used to
select which interconnections to use. 4 As explained above, that is not the
4 See, e.g., Ans. 7 ("[T]here is no direction about how to make a selection
using the random source. In other words, even if we assume that we have
the interconnections in place, and we have a random source (which produces
4
Appeal2015-005931
Application 11/387,401
case-the circuit is designed using randomly created connections. We are
not persuaded that the disclosure is deficient because it does not "provide the
steps of randomized algorithm which could include the conditions and steps
to determine how the random number source were selected to implement the
interconnections from two set of logic cells." (Ans. 8.) Instead, we
conclude that the Specification does provide the necessary steps, as it
discloses, for example, using as inputs to the first XOR gates (a) the NAND
outputs and (b) "randomly-selected bits from Co ... C1s, Ko ... Ki27, and U1
... U127." (Spec. 20:25-27.) One of skill in the art would have understood
how to select a bit from a set of bits randomly.
For these reasons, we do not sustain the rejection under 35 U.S.C.
§ 112, first paragraph.
DECISION
The rejection of claims 1-19 is reversed.
REVERSED
a random number, e.g. 5), there is nothing in the spec that describes how we
select an interconnection (or a set of interconnections) using number 5 in
hand.").
5