Ex Parte Koch et al

Patent Trial and Appeal Board

Mar 26, 2013

10521881 (P.T.A.B. Mar. 26, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte STEFAN MARCO KOCH, HANS-JOACHIM
GELKE, HARALD BAUER, and ARTHUR TRITTHART
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Appeal 2010-009393
Application 10/521,881
Technology Center 2100
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Before JOHN A. JEFFERY, DENISE M. POTHIER, and
JEREMY J. CURCURI, Administrative Patent Judges.

CURCURI, Administrative Patent Judge.

DECISION ON APPEAL1
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 1-7, 9, 10, and 13-19. Claims 8, 11, 12, and 20-23 are
canceled. Supp. Br. 2. We have jurisdiction under 35 U.S.C. § 6(b).

1 Rather than repeat the Examiner’s positions and Appellants’ arguments in
their entirety, we refer to the following documents for their respective
details: the Supplemental Appeal Brief (Supp. Br.) filed November 16, 2009;
the Examiner’s Answer (Ans.) mailed March 2, 2010; and the Reply Brief
(Reply Br.) filed April 28, 2010.
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Application 10/521,881

2
Claims 1-7, 9, 10, and 13-19 are rejected under 35 U.S.C. § 103(a) as
obvious over Koch (US 2002/0055979 A1; published May 9, 2002) and
Tang (US 6,775,717 B1; issued Aug. 10, 2004; filed June 21, 2002). Ans.
4-20.2
We affirm.

STATEMENT OF THE CASE
Appellants’ invention relates to inter-processor communication
between processors that are arranged on the same semiconductor die. Spec.
1:8-9. Claim 1 is illustrative and reproduced below:
1. A System comprising:
a first processor bus;
a first processor on a first clock coupled to the first processor bus;
a first direct memory access unit with a first external direct memory
access channel, the first direct memory access unit being coupled to the first
processor bus;
a first programmable unit comprising a first processor interface, the
first programmable unit coupled via the first external direct memory access
channel to the first direct memory access unit, said first programmable unit
being programmable by the first processor via the first processor interface;
a first shareable unit coupled to the first processor bus;
a second processor bus;
a second processor on a second clock coupled to the second processor
bus;

2 Due to the entered After-Final Amendment (see Advisory Action dated
April 15, 2009), we presume that the Examiner has withdrawn the § 102
rejection of claims 13, 14, 16, and 18-22 based on Koch. See Ans. 3-4.
Because we consider the rejection to have been withdrawn, we need not
address any arguments concerning the § 102 rejection found in the
November 26, 2008 Final Rejection. See Reply Br. 2.
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a second direct memory access unit with a second external direct
memory access channel, the second direct memory access unit being coupled
to the second processor bus;
a second programmable unit comprising a second processor interface,
the second programmable unit coupled via the second external direct
memory access channel to the second direct memory access unit, said
second programmable unit being programmable by the second processor via
the second processor interface; and
a second shareable unit being connected to the second processor bus,
wherein the first programmable unit and the second programmable
unit each comprises:
a direct access unit core;
a first external direct memory access channel interface on the
first clock; and
a second external direct memory access channel interface on the
second clock,
wherein a first bi-directional communication channel is established
between the first shareable unit and the second processor via the first
programmable unit, and a second bidirectional communication channel is
established between the second shareable unit and the first processor via the
second programmable unit.

ANALYSIS
Claims 1-7, 9, and 10
We agree with the Examiner’s position, with regard to claim 1, that
Koch and Tang collectively teach all claim limitations. Ans. 4-7. The
Examiner relies on Koch for all recited limitations except for the first and
second programmable units each comprising two external direct memory
access (DMA) channel interfaces, for which the Examiner relies on Tang.
Ans. 6-7 (citing Tang, col. 2, ll. 42-55).
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The Examiner reasons that it would have been obvious to one of
ordinary skill in the art at the time of the invention to include the dual DMA
channel interfaces taught by Tang in each of the programmable units taught
by Koch, including using the clock domain of each associated processor for
the associated DMA interfaces. Ans. 7 (citing Koch, ¶¶ 46, 56). The
Examiner explains that the motivation for doing so, provided by Tang,
would have been to reduce latency due to set up time between DMA
transfers. Id. (citing Tang, col. 2, ll. 42-55).
Appellants argue there is no suggestion in Tang that the DMA channel
interfaces are on separate clocks that also clock separate respective
processors coupled to separate buses. Supp. Br. 14. See also Reply Br. 2-4.
Appellants further argue that reducing the latency time between DMA
transfers would seem to motivate, if anything, adding a second channel
interface on a same clock, rather than adding a second channel interface on a
different clock. Supp. Br. 14.
In response, the Examiner explains Koch (Fig. 4) teaches connecting
two processors via DMA1 41 through programmable unit 51, and DMA2 54
through programmable unit 48. Ans. 21 (citing Koch, Fig. 4). The Examiner
further explains Koch teaches processor P1 and DMA1 41 (and unit 48’s
interface to P1’s bus) are on clock P1, while processor P2 and DMA2 54
(and unit 51’s interface to P2’s bus) are on a separate clock domain, clock
P2, where programmable units 48 and 51 serve to decouple the dataflow
from one processor from the clock of the other processor. Id. (citing Koch,
¶¶ 46, 56). The Examiner further explains it would have been obvious, in
light of Koch’s setup, when adding the second external channel to each
DMA as taught by Tang (connecting Koch’s DMA2 54 to programmable
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unit 51, and connecting Koch’s DMA1 41 to programmable unit 48), that the
added channels would be on the clock domains of their respective
processors. The Examiner further explains that, in Koch as modified by
Tang, the programmable units each have two external DMA channels with
each channel on its own clock domain, because the programmable units
serve to decouple clock domains from one another. Ans. 21-22 (citing Koch
¶¶ 46, 56). We agree with the Examiner.
Appellants have not persuaded us that Koch and Tang do not teach
each of the programmable units includes a first external DMA channel
interface on the first clock, and a second external DMA channel interface on
the second clock, as broadly recited in claim 1.
Regarding Appellants’ argument (Supp. Br. 14) that there is no
suggestion in Tang that the DMA channel interfaces are on separate clocks
that also clock separate respective processors coupled to separate buses, and
Appellants’ argument (id.) that reducing the latency time between DMA
transfers would not motivate adding a second channel interface on a
different clock, we find these arguments unavailing. See also Reply Br. 5-7.
The Examiner does not rely on Tang for teaching the use of separate
clocks. Rather, the Examiner reasonably explains why Koch suggests
decoupling clock domains and that when adding the second, external
channels as suggested by Tang, the added channels would be on the clock
domains of their respective processors. Ans. 21 (citing Koch, ¶¶ 46, 56).
Therefore, we see no reason why adding a second external channel to
each programmable unit 48, 51 (in light of Tang’s multiple DMA
interfaces), and the channels being on the clock domains of their respective
processors (in light of Koch’s teaching of decoupling clock domains) would
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not predictably use prior art elements according to their established
functions—an obvious improvement. See KSR Int’l Co. v. Teleflex Inc., 550
U.S. 398, 417 (2007).
We, therefore, sustain the Examiner’s rejection of claim 1, as well as
claims 2-7, 9, and 10, which are not separately argued with particularity.
Claims 13 and 16-19
We agree with the Examiner’s position, with regard to claim 13, that
Koch and Tang collectively teach all claim limitations. Ans. 9-14. The
Examiner relies on Koch for all recited limitations except for a second
external channel of each DMA unit contained within a second bi-directional
channel, for which the Examiner relies on Tang. Ans. 13 (citing Tang, col. 2,
ll. 42-55).
The Examiner reasons that it would have been obvious to one of
ordinary skill in the art at the time of the invention to include the dual DMA
channel interfaces taught by Tang in each of the programmable units taught
by Koch. Id. (citing Koch, ¶¶ 46, 56). The Examiner explains that the
motivation for doing so, provided by Tang, would have been to reduce
latency due to set up time between DMA transfers. Ans. 14 (citing Tang, col.
2, ll. 42-55).
Appellants have not persuaded us that Koch and Tang do not teach
first and second bi-directional channels, each comprising channels from first
and second DMA units, as broadly recited in claim 13.
Regarding Appellants’ argument (Supp. Br. 15) that there is no
suggestion in Koch that either bidirectional channel comprises an external
channel from both DMA1 41 and DMA2 54, we find this argument
unavailing because Appellants’ arguments are not germane to the purpose
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for which Koch was cited. The Examiner relies on Tang (Ans. 13 (citing
Tang, col. 2, ll. 42-55)) for teaching the second external channels of the
DMA units contained within the bi-directional channels, and reasonably
explains why Koch and Tang collectively teach all claim limitations.
Ans. 9-14.
Regarding Appellants’ argument (Supp. Br. 15) that adding a second
channel to either of the DMAs of Koch does not teach a bidirectional
channel comprising an external channel from two separate DMAs, we also
find this argument unavailing for reasons discussed above with respect to
similar limitations in claim 1, which recites each programmable unit
including first and second external DMA channel interfaces.
In short, we see no reason why adding the second external channel to
each DMA as taught by Tang to connect Koch’s DMA2 54 to programmable
unit 51, and connect Koch’s DMA1 41 to programmable unit 48, would not
predictably use prior art elements according to their established functions—
an obvious improvement. See KSR, 550 U.S. at 417.
We, therefore, sustain the Examiner’s rejection of claim 13, as well as
claims 16-19, which are not separately argued with particularity.
Claim 14
Appellants argue Koch and Tang do not teach a first bidirectional
channel comprising a first programmable unit coupled between the first
external channel of a first DMA unit and the first external channel of a
second DMA unit. Supp. Br. 16. Appellants also argue the Examiner does
not point to a second DMA unit or an external channel of a second DMA
unit. Id.
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Although the Examiner’s discussion for claim 14 (Ans. 14) does not
point to a second DMA unit or an external channel of a second DMA unit,
we nonetheless find Appellants’ arguments unpersuasive for reasons
discussed above with respect to similar limitations in claim 1, which recites
each programmable unit including first and second external DMA channel
interfaces. Notably, with regard to claim 1, the Examiner explains it would
have been obvious to add the second external channel to each DMA as
taught by Tang (connecting Koch’s DMA2 54 to programmable unit 51, and
connecting Koch’s DMA1 41 to programmable unit 48). Ans. 21-22.
Again, we see no reason why adding the second external channel to
each DMA as taught by Tang to connect Koch’s DMA2 54 to programmable
unit 51, and connect Koch’s DMA1 41 to programmable unit 48, would not
predictably use prior art elements according to their established functions—
an obvious improvement. See KSR, 550 U.S. at 417.
We, therefore, sustain the Examiner’s rejection of claim 14.
Claim 15
Appellants argue Koch and Tang do not teach a second programmable
unit coupled between the second external channel of the first DMA unit and
the second external channel of the second DMA unit, as recited in claim 15.
Supp. Br. 17.
We note claim 15 depends from claim 14 and further recites a second
programmable unit. The language in claim 15 for the second programmable
unit corresponds to the language in claim 14 for the first programmable unit.
We are not persuaded of error for reasons discussed above with respect to
claim 14.
We, therefore, sustain the Examiner’s rejection of claim 15.
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ORDER
The Examiner’s decision rejecting claims 1-7, 9, 10, and 13-19 is
affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1).

AFFIRMED

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