Ex Parte Ko et al

Patent Trial and Appeal Board

Mar 31, 2016

12842546 (P.T.A.B. Mar. 31, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
12/842,546 07/23/2010
43859 7590 04/04/2016
SLATER MATSIL LLP
17950 PRESTON ROAD, SUITE 1000
DALLAS, TX 75252
FIRST NAMED INVENTOR
Chih-Hsin Ko
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
TSM09-0447 4297
EXAMINER
KUSUMAKAR, KAREN M
ART UNIT PAPER NUMBER
2897
NOTIFICATION DATE DELIVERY MODE
04/04/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
docketing@slatermatsil.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte CHIH-HSIN KO and CLEMENT HSINGJEN WANN
Appeal2014-001402
Application 12/842,546
Technology Center 2800
Before ADRIENE LEPIANE HANLON, CATHERINE Q. TIMM, and
JAMES C. HOUSEL, Administrative Patent Judges.
TIMM, Administrative Patent Judge.
DECISION ON APPEAL 1
STATEMENT OF CASE
Appellants2 appeal the Examiner's decision to reject claims 1-12 and
14--19 under 35 U.S.C. §103(a). Specifically, the Examiner rejects claims 1,
1 In our opinion below, we refer to the Specification filed July 23, 2010
(Spec.), Final Office Action mailed February 26, 2013 (Final), the Appeal
Brief filed July 24, 2013 (Appeal Br.), the Examiner's Answer mailed
August 22, 2013 (Ans.), and the Reply Brief filed October 22, 2013 (Reply
Br.).
2 Appellants' identify the real party in interest as Taiwan Semiconductor
Manufacturing Co., Ltd. ("TSMC"). Appeal Br. 3.
Appeal2014-001402
Application 12/842,546
2, 4, 5, and 7-9 as obvious over Bai3 in view of AAPA, 4 and claims 3, 6, 10-
12, and 14--9 as obvious over those references further in view of Sunakawa.5
We have jurisdiction under 35 U.S.C. §§ 6(b) and 134(a).
We AFFIRM.
The claims are directed to a method of forming an integrated circuit
structure. Claim 1, with emphasis on the limitation at issue in the appeal, is
illustrative:
1. A method of forming an integrated circuit structure,
the method comprising:
providing a silicon substrate;
forming a plurality of shallow trench isolation (STI)
regions in the silicon substrate;
forming recesses by removing top portions of the silicon
substrate between opposite sidewalls of the plurality of S TI
regions, wherein substantially all long sides of all recesses in
the silicon sitbstrate extend in a same direction; and
epitaxially growing a III-V compound semiconductor
material in the recesses.
Claims Appendix, Appeal Br. 20 (emphasis added).
OPINION
There is no dispute that it was known in the art to form recesses in the
STI regions of a silicon substrate and epitaxially grow a III-V compound
semiconductor material in the recesses. Spec. i-fi-13--4. The question is
3 Bai et al., US 2008/0099785 Al, pub. May 1, 2008.
4 Applicants' Admitted Prior Art, Spec. i-fi-1 3 and 4.
5 Sunakawa et al., US 2002/0066403 Al, pub. Jun. 6, 2002.
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Appeal2014-001402
Application 12/842,546
whether Appellants have identified a reversible error in the Examiner's
determination that, based on the teachings of Bai, the ordinary artisan would
have extended all the long sides of all the recesses in the same direction. For
the reasons provided by the Examiner in the Answer and the reasons below,
we determine that Appellants have not identified such an error.
The Examiner finds that Bai teaches forming recesses in the same
direction, citing to paragraph 54 of Bai. Final 2-3. Appellants contend that
paragraph 54 does not support the Examiner's finding. According to
Appellants, Bai fails to distinguish the long sides from the short sides of the
trenches, and fails to realize that aligning the long side and the shorts sides
in certain directions makes a difference. Appeal Br. 12-13 and 16-17.
We do not find Appellants' arguments persuasive because they fail to
take into account the totality of the teachings of Bai as that reference would
have been read by one of ordinary skill in the art.
Bai is directed to a method of blocking defects by aspect ratio
trapping (ART). Bai i12. Aspect ratio trapping is a technique of causing
defects to terminate at dielectric sidewalls where the sidewalls are
sufficiently high relative to the size of the growth area to trap most, if not all,
of the defects. Bai i-f 6. These defects occur during the epitaxial growing of
a lattice-mismatched material, such as an III-V compound semiconductor
like GaAs, in a trench on a substrate such as silicon. Bai i-fi-12-5, 40, and 44--
45.
Contrary to Appellants' arguments, Bai distinguishes long sides from
short sides. Bai grows the lattice-mismatched material (e.g., second
crystalline semiconductor material 140 of Figs. 1 and 5B) in a trench having
a width w smaller than a length 1. Bai i-fi-143, 59. Bai is especially concerned
with the ratio of the height of the trench to the width of the trench. Bai i-f 7.
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Appeal2014-001402
Application 12/842,546
This ratio must be such that, as the crystal grows, defects 150 propagate
away from the longitudinal axis (e.g., axis 500 in Fig. 5B) and are trapped
by the sidewall of the long side of the trench as shown in Figures 5A and 5B.
Bai i-fi-157-59; see also Figs. 1 and 3. Bai teaches orienting the sidewalls so
that glissile threading dislocations are trapped solely due to their
crystallographic geometry, i.e., their preferred orientation after experiencing
glide. Bai i1 49. Bai controls another type of threading dislocation, which
Bai calls growth dislocations, by controlling crystal growth. Bai i-fi-150-53.
Specifically, Bai epitaxially grows second crystalline material 140 to cause
facets (e.g., facets 310 in Fig. 3) to form in a way that directs the growth
dislocations 320 towards the sidewall 130. Bai i-fi-151-53; Fig. 3. Bai
specifically teaches orienting the sidewalls in a specific direction to trap the
defects. Bai ,-r 48, 49, ,-r 54, ,-r 57.
Epitaxially growing III-V compound semiconductors in trenches
according to the teachings of Bai involves forming the trenches with all long
sides (e.g., sidewalls of length l in Fig. 5B) extending in the same direction.
This is necessary in order to align the crystal surface of the silicon and the
crystal lattice of the growing crystal of the III-V compound semiconductor
so that, as the IIII-V compound semiconductor grows, the defects are
trapped by the ART process of the reference.
Appellants contend that paragraph 54 only discloses orienting vertical
sidewall openings 200nm and larger along the [110] direction, and does not
disclose how to orient all openings with widths smaller than 200 nm.
Appeal Br. 12; Reply Br. 5. But Appellants' argument fails to consider the
disclosure of paragraph 54 in its proper context. Paragraph 54 discloses an
experimental procedure:
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Appeal2014-001402
Application 12/842,546
More specifically, the following experimental conditions
were used to engineer facets to effectively direct growth
dislocation segments to the sidewalls. Starting with a Si (001)
substrate having a 500 nm-thick thermal oxide overlayer
patterned with vertical sidewall openings 200 nm wide and
larger, oriented along the [110] direction, Ge layers were
grown using a two-step process including growth of a low-
temperature buffer layer at 400° C. and growth of a second
layer at a higher temperature of 600° C. For the purpose of
delineating facet evolution, SiGe marker layers of
approximately 10%-15% Si content were periodically inserted.
This step is not required for the ART technique, but was done
merely for the purposes of elucidating the process. For analysis,
cross-sectional and plan-view transmission electron microscopy
(TEM) specimens were prepared by mechanical thinning
followed by Ar ion-milling. TEM analysis was conducted on a
JEOL JEM 2100 microscope.
Bai i-f 54 (emphasis added). The phrase "vertical sidewall openings 200 nm
wide and larger" merely denotes the width of the openings that were formed
and tested. It is does not imply that there were other openings in other
orientations. Considering the teachings of Bai as a \~1hole, it becomes clear
that Bai teaches orienting all the trenches to be filled with epitaxially grown
lattice mismatched semiconductor material in the same direction. This is
necessary to successfully trap the defects.
In response to Appellants' arguments, the Examiner further cited Oda6
and Kitada.7 Final 9-10; Ans. 4--5. The teachings of these references, while
not necessary to the rejection, further support the findings and conclusions
of the Examiner.
Appellants contend that aligning all long sides in the same direction
has unexpected results as explained in paragraphs 18-20 of their
6 Oda et al., US 2001/0045604 Al, pub. Nov. 29, 2001.
7 Kitada et al., US 2003/0042555 Al, pub. Mar. 6, 2003.
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Appeal2014-001402
Application 12/842,546
Specification. Appeal Br. 15-16. Paragraphs 18-20 of the Specification
merely explain the epitaxial growth process of GaAs crystals, and how
defects grow to join the sidewalls of the long sides of the recesses.
As stated in In re Freeman:
In order for a showing of "unexpected results" to be
probative evidence of non-obviousness, it falls upon the
applicant to at least establish: ( 1) that there actually is a
difference between the results obtained through the claimed
invention and those of the prior art, ... and (2) that the
difference actually obtained would not have been expected by
one skilled in the art at the time of invention.
In re Freeman, 474 F.2d 1318, 1324 (CCPA 1973) (citations omitted).
Appellants have not pointed to any objective evidence showing a
difference between the results obtained through the claimed invention as
compared to the closest prior art, i.e., Bai, much less established that the
difference would have been unexpected to one of ordinary skill in the art.
Turning to the rejection of claims 3, 6, 10-12, and 14--9, in which the
Examiner added Sunakawa to support the obviousness of additional
limitations, Appellants add no new arguments. Appeal Br. 17-18. For the
reasons we explain above, Appellants have not identified a reversible error
in the Examiner's rejection of claims 3, 6, and 10-19.
CONCLUSION
We sustain the Examiner's rejections.
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Appeal2014-001402
Application 12/842,546
DECISION
The Examiner's decision is affirmed.
TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l).
AFFIRMED
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