Ex Parte Ko et al

Patent Trial and Appeal Board

Jul 26, 2016

12232019 (P.T.A.B. Jul. 26, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
12/232,019 09/10/2008 Cheng-Ta Ko
31561 7590 07/28/2016
JIANQ CHYUN INTELLECTUAL PROPERTY OFFICE
7 FLOOR-I, NO. 100
ROOSEVELT ROAD, SECTION 2
TAIPEI, 100
TAIWAN
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
49979-US-PA 6240
EXAMINER
GUPTA,RAJR
ART UNIT PAPER NUMBER
2829
NOTIFICATION DATE DELIVERY MODE
07/28/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
USA@JCIPGROUP.COM.TW
Belinda@JCIPGROUP.COM.TW
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte CHENG-TA KO and SU TSAI LU
Appeal2014-008458
Application 12/232,019
Technology Center 2800
Before JAMES R. HUGHES, LINZY T. McCARTNEY, and
MELISSA A. RAAP ALA, Administrative Patent Judges.
RAAP ALA, Administrative Patent Judge.
DECISION ON APPEAL
This is a decision on appeal under 35 U.S.C. § 134(a) from a final
rejection of claims 1, 3, 4, 6-8, and 18. 1 We have jurisdiction under 35
U.S.C. § 6(b).
We affirm.
1 Claims 2, 5, and 9-17 have been withdrawn, and claim 19 has been
canceled.
Appeal2014-008458
Application 12/232,019
EXEivIPLAR Y CLAiivI
Claim 1 is exemplary of the subject matter on appeal:
1. A three-dimensional (3D) chip-stack package, adapted
to be disposed on a printed circuit board (PCB) having a plurality
of conductive contacts, the 3D chip-stack package comprising:
a component-embedded plate, comprising
a dielectric layer having a first surface and a second
surface, wherein a plurality of first soldering balls are
disposed on the first surface;
an active component embedded in the second
surface of the dielectric layer, one surface of active
component being exposed outside the dielectric layer, the
active component having a plurality of TSV s (Through
Silicon Via), each of the plurality of TS Vs extending from
the exposed surface of the active component through the
active component and the dielectric layer, such that one
end of each of the plurality of TSV s is exposed outside of
the surface of the active component; and
an electrical circuit on the dielectric layer and in
electrical connection between the other end of the plurality
of TSV s of the active component and the first soldering
balls, respectively,
wherein the component-embedded plate and the
PCB is connected only by the first soldering balls; and
a side integrated circuit (IC) having a plurality of pads, the
pads electrically connected with the exposed ends of the plurality
of TSVs of the active component, wherein the component-
embedded plate and the side IC define a first gap therebetween,
and the component-embedded plate and the PCB define a second
gap therebetween.
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Appeal2014-008458
Application 12/232,019
REJECTIONS ON APPEAL
Claims 1, 3, 4, 7, and 8 stand rejected under 35 U.S.C. § 103(a) as
being obvious over the combination of Sunohara (US 2004/0113261 Al;
June 17, 2004) and Umetsu (US 2002/0127839 Al; Sept. 12, 2002).
Claims 6 and 18 stand rejected as being unpatentable under 35 U.S.C.
§ 103(a) over the combination ofSunohara, Umetsu, Trieu (US 6,479, 890
Bl; Nov. 12, 2002), and Owens (US 2004/0129452 Al; July 8, 2004).
ANALYSIS
Appellants contend the combination of Sunohara and Umetsu does not
teach or suggest the component-embedded plate and the PCB define a
second gap ("second gap" limitation) and the component-embedded plate
and the PCB is connected only by the first soldering balls ("connected by"
limitation), as recited in independent claim 1. App. Br. 5. In particular,
Appellants argue that in Sunohara, no gap exists between the semiconductor
chip 20 and the base substrate 30 because it is occupied by underfill resin 18.
App. Br. 6; see also Reply Br. 1-2. Appellants also argue that Sunohara
fails to satisfy the "connected by" limitation because insulating film 34a is
disposed on the wiring substrate 40 so that it is not connected to the PCB
only by soldering balls. App. Br. 9; see also Reply Br. 5. Additionally,
Appellants argue the combination of Sunohara and Umetsu is improper
because the packaging structures are different, replacing the underfill resin
18 of Sunohara with the gap taught by Umetsu would teach away from the
structure of Sunohara (which requires the underfill resin 18 to be formed),
and the combination would result in an incomplete packaging structure with
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Appeal2014-008458
Application 12/232,019
the second interlayer insulating film 34a unable to be formed. App. Br. 7-8;
see also Reply Br. 3--4.
Appellants' arguments that Sunohara does not teach the "second gap"
and "connected by" limitations are not persuasive because the Examiner
relies on Umetsu, not Sunohara to teach these limitations. See Ans. 3--4.
We agree with the Examiner that Umetsu illustrates a gap between
semiconductor device 1 (equated by the Examiner to be the claimed
"component embedded plate") and PCB 80, and thus teaches the "second
gap" limitation. See Umetsu, Fig. 10. We further agree that Umetsu
illustrates that the semiconductor device 1 (component embedded plate) and
PCB 80 are connected only be external terminals 90 (soldering balls 90),
which teaches the "connected by" limitation. See id.
We are also not persuaded by Appellants' arguments that the
combination is improper. Sunohara and Umetsu are both directed to
semiconductor devices. See Suohara i-fi-128-29, Fig. II; Umetsu i13, Figs 3,
10. We agree with Appellants that Sunohara describes that underfill resin 18
is filled into the clearances (gap) between the semiconductor chip 20 and the
wiring substrate 40. App. Br. 5---6; see Sunohara, i128, Fig. II. However,
we disagree with Appellants that Sunohara teaches away from replacing the
underfill resin 18 with the gap taught by Umetsu. To teach away, a
reference must "criticize, discredit, or otherwise discourage" investigation
into the claimed solution. In re Fulton, 391 F.3d 1195, 1201 (Fed. Cir.
2004 ). Appellants have not provided sufficient evidence to show that
Sunohara criticizes, discredits, or otherwise discourages a gap between the
semiconductor chip 20 and the wiring substrate 40. Although Sunohara's
particular method of manufacture uses underfill resin in the formation of the
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Appeal2014-008458
Application 12/232,019
semiconductor device, we agree with the Examiner that the disputed claims
are directed not to a method of formation, but to the final structure of the
device. See Ans. 6-7. Appellants do not provide sufficient persuasive
argument or evidence to rebut the Examiner's findings that one of ordinary
skill in the art would not be required to follow the method of formation
described in Sunohara, but would have other options to form the device with
the gap taught by Umetsu. See Ans. 7.
The Examiner cites Sunohara for the teaching of a chip-stack package
including an active component and TSV s, and cites Umetsi for the
connection arrangement utilizing soldering balls. Id. Appellants do not
provide sufficient persuasive argument or evidence to show that combining
these known prior art structural features would have been uniquely
challenging or beyond the skill of an ordinarily skilled artisan. See KSR Int 'l
Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007) ("[I]f a technique has been
used to improve one device, and a person of ordinary skill in the art would
recognize that it would improve similar devices in the same way, using the
technique is obvious unless its actual application is beyond his or her skill"
(citations omitted)). We are not persuaded that combining the respective
familiar elements of the cited references in the manner proffered by the
Examiner would have been "uniquely challenging or difficult for one of
ordinary skill in the art" at the time of Appellants' invention. Leapfrog
Enters., Inc. v. Fisher-Price, Inc., 485 F.3d 1157, 1162 (Fed. Cir. 2007)
(citing KSR, 550 U.S. at 418).
For the reasons stated above, Appellants fail to persuade us of error in
the rejection of claim 1. Accordingly, we sustain the 35 U.S.C. § 103(a)
rejections of claim 1 and its dependent claims 3, 4, 6-8, and 18, for which
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Appeal2014-008458
Application 12/232,019
Appellants does not present separate arguments for patentability (see App.
Br. 9).
DECISION
We affirm the Examiner's decision to reject claims 1, 3, 4, 6-8, and
18.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 41.50(±).
AFFIRMED
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