Ex Parte Knowles

Patent Trial and Appeal Board

Oct 29, 2014

10813615 (P.T.A.B. Oct. 29, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD

____________

Ex parte SIMON KNOWLES
____________

Appeal 2010-012209
Application 10/813,615
Technology Center 2100
____________

Before CARLA M. KRIVAK, JASON V. MORGAN, and
JOHHNY A. KUMAR, Administrative Patent Judges.

KRIVAK, Administrative Patent Judge.

DECISION ON APPEAL
Appellant appeals under 35 U.S.C. § 134(a) from a final rejection of
claims 1–6, 8–18, and 21. We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.

Appeal 2010-012209
Application 10/813,615

2
STATEMENT OF THE CASE
Appellant’s claimed invention is directed to “a computer processor, a
method of operating the same, and a computer program product comprising
an instruction set for the computer” (Spec. 1:4–5).
Independent claim 1, reproduced below, is representative of the
subject matter on appeal.
1. A computer processor for processing (i) instruction
packets comprising a plurality of only control instructions, the
control instructions having a control bit width, and (ii)
instruction packets comprising a plurality of instructions
comprising at least one data processing instruction, the data
processing instructions having a data processing bit width wider
than the control bit width, the processor comprising:

a decode unit for decoding sequentially the instruction
packets fetched from a memory holding the instruction packets,
the instruction packets being all of equal bit length;

a control processing channel capable of performing
control operations, the control processing channel comprising a
plurality of functional units including a control register file
having a first bit width; and

a data processing channel capable of performing data
processing operations at least one input of which is a vector, the
data processing channel comprising a plurality of functional
units including a data register file having a second bit width,
wider than the first bit width;

wherein the decode unit comprises decode circuitry
configured to decode identification bits of each instruction
packet to determine which type (i), (ii), of instruction packet is
being decoded, and control circuitry configured to pass the
plurality of only control instructions having the control bit
width from an instruction packet of type (i) to the control
processing channel when the decode circuitry indicates so and
Appeal 2010-012209
Application 10/813,615

3
to pass the plurality of instructions comprising at least one data
processing instruction having the data processing bit width
wider than the control bit width from an instruction packet of
type (ii) to the data processing channel when the decode
circuitry indicates so;

wherein, in use the decode unit causes instructions of
(i) instruction packets comprising a plurality of only control
instructions to be executed sequentially on the control
processing channel; and

wherein, in use the decode unit causes instructions of
(ii) instruction packets comprising a plurality of instructions
comprising at least one data processing instruction to be
executed simultaneously on the data processing channel.

REFERENCES and REJECTIONS
The Examiner rejected claims 1–6, 11, 14–18, and 21 under 35 U.S.C.
§ 103(a) based upon the teachings of Hull (US 5,922,065, July 13, 1999),
Bolotski (Michael Bolotski et al., Unifying FPGAs and SIMD Arrays, MIT
Transit Project (1994)), and Hennessey (John Hennessy & David Patterson,
Computer Architecture: A Quantitative Approach, 127–130, D-1–D-14
(2003)).
The Examiner rejected claims 8–10, 12, and 13 under 35 U.S.C.
§ 103(a) based upon the teachings of Hull, Hennessy, Bolotski, and In re
Rose, 220 F.2d 459 (CCPA 1955).

ANALYSIS
Appellant argues Hull does not teach or suggest the claimed processor
having a decode unit as claimed; rather, Hull teaches a processor used for
encoding (App. Br. 9).
Appeal 2010-012209
Application 10/813,615

4
The Examiner states Hull was cited to teach “instructions in bundles
with lower memory addresses are considered to precede instructions in
bundles with higher memory addresses” (Ans. 17–18). The Examiner
further states Hull does not explicitly recite a decoder, but one of ordinary
skill in the art would recognize decoders are inherent in all computers (Ans.
17). Further, Hull operates on instructions (from a decoder) and discloses
the functionality of a decoder by teaching instructions are considered in
sequential order determined by their memory address, thus reading on
Appellant’s decoder (Ans. 18). The Examiner further finds Hull’s column 2,
lines 5–8, teaches this limitation by stating “the present invention provides a
processor capable of simultaneously executing a plurality of sequential
instructions [with a highly efficient encoding of instructions]” (Ans. 20).
We agree with Appellant the Examiner has not shown how Hull, or
any other of the cited references, teaches or suggests different instruction
packets handled differently by a decode unit, as claimed. Although the
Examiner finds all computers have a decoder, the Examiner has not shown,
on this record, the manner in which the decode unit operates on the different
types of data (“instruction packets comprising a plurality of only control
instructions to be executed sequentially on the control processing channel”
and “instruction packets comprising a plurality of instructions comprising at
least one data processing instruction to be executed simultaneously on the
data processing channel” (claim 1)) (Reply Br. 6–7). Additionally, we agree
column 2, lines 5–8 of Hull does not teach or suggest “(1) a decode unit, (2)
causing instructions including at least one data processing instruction, (3) to
be executed simultaneously on a data processing channel” (App. Br. 11).
Appeal 2010-012209
Application 10/813,615

5
The Examiner has not shown how the additionally cited references
cure the deficiencies of Hull. Thus, on this record, we are constrained to
find the cited references do not teach or suggest Appellant’s claimed
limitations. We therefore do not sustain the Examiner’s rejection of
independent claims 1, 18, and 21, argued for substantially the same reasons,
and claims 2–6 and 8–17, dependent therefrom.

DECISION
The Examiner’s decision rejecting claims 1–6, 8–18, and 21 under
35 U.S.C. § 103 is reversed.

REVERSED

msc