Ex Parte Kleihorst et al

Patent Trial and Appeal Board

Oct 24, 2012

10479089 (P.T.A.B. Oct. 24, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
_____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
_____________

Ex parte RICHARD PETRUS KLEIHORST,
ADRIANUS JOHANNES MARIA DENISSEN,
ANDRE KRIJN NIEUWLAND, and NICO FRITS BENSCHOP
_____________

Appeal 2010-005209
Application 10/479,089
Technology Center 2100
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Before KALYAN K. DESHPANDE, BRYAN F. MOORE, and
RAMA G. ELLURU Administrative Patent Judges.

MOORE, Administrative Patent Judge.

DECISION ON APPEAL

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This is a decision on appeal under 35 U.S.C. § 134(a) of the
Examiner’s Final Rejection of claims 1, 9, and 11-28. App. Br. 2. Claims 2-
8 and 10 are cancelled. We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM-IN-PART.

INVENTION
The invention is directed to a method for error detection in
digital circuits using the digital system. See Spec. p.1, ll. 1-3.

Claim 1 is representative of the invention and is reproduced
below:
1. A digital system, the digital system having a
digital input vector, the digital system comprising:
a first terminal for receiving the digital input vector;
a digital processing unit coupled to the first input
terminal, the digital processing unit processing the digital input
vector, the digital processing unit comprising a Module under
Test, the Module under Test having a second input terminal
coupled to the first input terminal and having a second output
terminal, the Module under Test being responsive to the digital
input vector by (a) providing a responsive digital vector in
response to the digital input vector;
an Actual Parity Generator having a third input terminal
coupled to the second output terminal and having a third output
terminal, the Actual Parity Generator providing, at the third
output terminal, an actual parity signal representing the parity
of the responsive digital vector;
a State Parity Generator having a sixth input terminal
coupled to the first input terminal and having a sixth output
terminal, the State Parity Generator arranged to provide (a)
responsive to the digital input vector causing the Module under
Test to enter at least one used state, a representative parity
signal representative of the parity of an errorless digital vector
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predetermined for at least one used state of the Module under
Test and (b) responsive to the digital input vector causing the
Module under Test to enter at least one unused state, a selected
signal characterizing the unused state; and
a comparator having a seventh output terminal, having a
fourth input terminal coupled to the third output terminal for
receiving the actual parity signal and having a fifth input
terminal coupled to a sixth output terminal for receiving the
representative parity signal, the comparator realizing a digital
comparison between the actual parity signal and the
representative parity signal and providing a comparator output
signal at the seventh output, the comparator output signal
terminal being a function of the realized digital comparison and
the selected signal and indicative of a potential error associated
with the Module under Test.

REFERENCES
Kurihara US 4,107,649 Aug. 15, 1978
Baun, Jr. US 4,251,884 Feb. 17, 1981
Caprasse US 4,884,273 Nov. 1989
Grove US 5,857,103 Jan. 5, 1999

REJECTIONS AT ISSUE
Claims 22 and 23 stand rejected as unpatentable under 35 U.S.C.
§ 102(b) as being anticipated by Kurihara. Ans. 3-5.
Claims 1, 9, 11-16, 18-21, 24-26 and 28, stand rejected as
unpatentable under 35 U.S.C. § 103(a) as being obvious over the
combination of Kurihara and Grove. Ans. 7-15.
Claims 17 and 27 stand rejected as unpatentable under 35 U.S.C.
§ 103(a) as being obvious over the combination of Kurihara, Grove, and
Baun. Ans. 15-16.
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Claims 22 and 23 stand rejected as unpatentable under 35 U.S.C.
§ 102(b) as being anticipated by Caprasse. Ans. 5-6.

ISSUE
1. Did the Examiner incorrectly determine that Kurihara discloses
“causing the Module under Test to enter at least one unused state, a selected
signal characterizing the unused state” recited in claim 1?
1

2. Did the Examiner incorrectly determine that Caprasse discloses
“Module under Test” recited in claim 22?
ANALYSIS
35 U.S.C. § 103(a) – Kurihara and Grove
Claim 1, 9, 11-16, 18-21, 24-26 and 28
Appellants’ arguments have persuaded us of error in the Examiner’s
rejection of claims 1, 9, 11-16, 18-21, 24-26, and 28.
Claim 1 recites “causing the Module under Test to enter at least one
unused state, a selected signal characterizing the unused state.” The
Examiner finds that, in the Specification, “for an input sequence (p_lnV),
there is a corresponding output state of the module under test (State) [and] . .
. that for some input sequences . . . , there is no corresponding function of
the module under test and therefore no meaningful output state (represented
by don’t care values x).” Ans. 17. Based on this finding, the Examiner
further finds that “Grove teaches in col. 3, lines 50-52 that for an input
instruction sequence, a processor has a corresponding output state.

1
Appellant make additional arguments regarding representative claim 1.
App. Br. 6-10. We do not reach these additional issues since this issue is
dispositive of claim 1.
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However, Grove makes it clear that there are some input instruction
sequences for which there are no corresponding functions of the processor.
These are the unused states of Grove.” Id. The Examiner’s further findings
are unsupported.
Appellants argue that “[c]ol. 3:50-52 of the ’103 reference mentions
using otherwise unused bits to address additional registers, however, this
comment does not correspond to an unused state of a module under test.”
App. Br. 5. Specifically, Appellants argue “a few unused bits of an
instruction bear no corresponding relationship to an unused state of a module
under test (e.g., data bits are not a state per se and used states can receive
some input bits that are not used).” Id. We are persuaded by this argument.
Claim 1 specifically requires “digital input vector causing the Module
under Test to enter at least one unused state.” Grove does not disclose that
“a processor has a corresponding output state” or unused states, as suggested
by the Examiner. Grove “utilizes unused bits in the instruction set to
address additional registers available on the processor.” Grove, col. 3, ll. 51-
52. The Examiner has not explained, nor do we discern, how one would use
unused bits in an input instruction sequence, which relates to instructions for
an executable program, to arrive at the claimed unused state caused by
digital input vector. The Examiner simply suggests that because the state of
a module is expressed in bits and an instruction word is expressed in bits,
these things must be related. This argument is not persuasive. Thus, we do
not sustain the Examiner’s rejection of claim 1.
For the reasons stated above, we do not sustain the Examiner’s
35 U.S.C. § 103(a) rejection of independent claim 1, independent claim 9,
and dependent claim 24 which contain essentially the same limitation as
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discussed above. Claims 11-16, 18-21, 24-26, and 28 depend from claims
1, 9, and 24, and thus we do not sustain the Examiner’s rejection of those
claims.
35 U.S.C. § 103(a) – Kurihara, Grove, and Baun
17 and 27
Claim 17 depends from claim 1, therefore, for the same reasons as
discussed supra, we do not sustain the Examiner’s 35 U.S.C. § 103(a)
rejection of claim 17.
The Examiner’s rejection of claim 27 under 35 U.S.C. § 103(a) as
unpatentable over Kurihara, Grove, and Baun refers to the same sections of
Grove to show essentially the same limitations as the one discussed supra.
See Ans. 9-20. For the same reasons as discussed supra, we do not sustain
the Examiner’s 35 U.S.C. § 103(a) rejection of claim 27.
35 U.S.C. § 102(b) – Kurihara
22 and 23
Appellants have not presented arguments regarding the Examiner’s
rejection of claims 22-23 as anticipated by Kurihara. As such, the
Appellants have waived arguments towards this rejection and accordingly
we summarily affirm this rejection.
35 U.S.C. § 102(b) – Caprasse
22 and 23
As noted above, we summarily affirm the Examiner’s decision to
reject claims 22 and 23 under 35 U.S.C. § 102(b) as being anticipated by
Kurihara. Therefore, we decline to reach the cumulative rejection of claims
22 and 23 under 35 U.S.C. § 102(b) as being anticipated by Caprasse.
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DECISION
The Examiner’s decision to reject claims 22 and 23 as anticipated by
Kurihara is summarily affirmed. We do not reach the merits of the
Examiner’s decision to reject claims 22 and 23 as anticipated by Caprasse.
The Examiner’s decision to reject claims 1, 9, 11-17, 18-21, and 24-28 is
reversed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1). See 37 C.F.R.
§ 1.136(a)(1)(iv) (2011).

AFFIRMED-IN-PART

ELD